Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Automatic A/D converter operation using a programmable control table

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Radio transmitter IQ imbalance measurement and correction methods and apparatus

Abstract: Embodiments include transceivers and transmit IQ imbalance correction methods. A transmitter lineup, which includes an equalizer and an RF modulator, receives a stream of baseband samples having real and imaginary components, processes the real components along a first channel, and processes the imaginary components along a second channel to produce processed real and imaginary components. The equalizer equalizes at least one of the processed real components and the processed imaginary components to compensate for offset frequency-dependent components of transmitter IQ imbalance. The RF modulator receives and modulates analog versions of the equalized samples, resulting in an analog RF signal. An embodiment also includes a balancer adapted to apply IQ gain and phase correction to the equalized samples to compensate for offset frequency-independent components of the transmitter IQ imbalance. A calibration processing subsystem determines filter coefficients used by the equalizer and IQ gain and phase correction values used by the balancer.

Method of blocking a void during contact formation process and device having the same

Abstract: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.

Method for forming a dual gate oxide device using a metal oxide and resulting device

Abstract: A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage requirements, e.g. an I/O region (24). A thinner second gate dielectric (20) is formed in a region of the device for lower voltage requirements, e.g. a core device region (22). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide (26) is deposited over both dielectrics, followed by deposition of a gate electrode material (28). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Encryption apparatus with diverse key retention schemes

Abstract: An encryption apparatus ( 14 ) includes a secure processing system ( 12 ) in the form of an integrated circuit. The secure processing system ( 12 ) includes an on-chip secure memory system ( 30 ). The secure memory system ( 30 ) includes a non-volatile, read-only, permanent key register ( 62 ) in which a permanent cryptographic key ( 64 ) is stored. The secure memory system ( 30 ) also includes a non-volatile, read-write, erasable key register ( 56 ) in which an erasable cryptographic key ( 60 ) is stored. Symmetric cryptographic operations take place in an encryption engine ( 46 ) using an operating cryptographic key ( 68 ) formed by combining ( 96 ) the permanent and erasable keys ( 64, 60 ). A tamper detection circuit ( 70 ) detects tampering and erases the erasable key ( 60 ) when a tamper event is detected.