Hewlett-Packard

About: Hewlett-Packard is a company organization based out in Palo Alto, California, United States. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 34663 authors who have published 59808 publications receiving 1467218 citations. The organization is also known as: Hewlett Packard & Hewlett-Packard Company.

FAB: building distributed enterprise disk arrays from commodity components

Abstract: This paper describes the design, implementation, and evaluation of a Federated Array of Bricks (FAB), a distributed disk array that provides the reliability of traditional enterprise arrays with lower cost and better scalability. FAB is built from a collection of bricks, small storage appliances containing commodity disks, CPU, NVRAM, and network interface cards. FAB deploys a new majority-voting-based algorithm to replicate or erasure-code logical blocks across bricks and a reconfiguration algorithm to move data in the background when bricks are added or decommissioned. We argue that voting is practical and necessary for reliable, high-throughput storage systems such as FAB. We have implemented a FAB prototype on a 22-node Linux cluster. This prototype sustains 85MB/second of throughput for a database workload, and 270MB/second for a bulk-read workload. In addition, it can outperform traditional master-slave replication through performance decoupling and can handle brick failures and recoveries smoothly without disturbing client requests.

High-speed and low-energy nitride memristors

Abstract: High-performance memristors based on AlN films have been demonstrated, which exhibit ultrafast ON/OFF switching times (≈85 ps for microdevices with waveguide) and relatively low switching current (≈15 μA for 50 nm devices). Physical characterizations are carried out to understand the device switching mechanism, and rationalize speed and energy performance. The formation of an Al-rich conduction channel through the AlN layer is revealed. The motion of positively charged nitrogen vacancies is likely responsible for the observed switching.

Path recovery on failure in load balancing switch protocols

Abstract: A method for managing multiple active paths among a plurality of network switches to identify and select an alternate path in response to failure of a path from a switch to a device Load balancing protocols of the present invention enable the simultaneous use of multiple paths between network devices through a mesh of compliant network switches When a port of a network switch fails (or the link connected to a port fails), a switch in accordance with the present invention selects an alternate port which may be used for forwarding packets to devices normally reached through the failed port Networks switches operable in accordance with the structures and protocols of the present invention exchange messages to identify potential alternate paths A potential alternate path is used to send a query message to a neighboring network switch to determine if a path to the identified devices is available through the neighboring network switch Such query messages are propagated through all intermediate network switches between the switch sensing the failed port up to the identified network device Acknowledgment messages are returned to verify potential availability of an alternate path Where an intermediate network switch determines that the complete path is not available through it to the identified device, or where a potentially better path exists, a regenerated query message so indicating is returned along the path that initiated the query message

Core architecture optimization for heterogeneous chip multiprocessors

Abstract: Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.

Multi-server fault tolerance using in-band signalling

Abstract: A primary server/standby server network configuration according to the invention includes a primary server executing network operating system software and a standby server monitoring for the proper operation of the primary server, where both the primary server and the standby server are connected to a storage system. If the primary server fails, the standby server instructs the storage system to switch its hardware connections to the standby server, allowing the standby server to boot the operating system. This instruction is done via in-band signaling. Further, multiple primary servers can be backed up by a single standby server.