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Institution

Hewlett-Packard

CompanyPalo Alto, California, United States
About: Hewlett-Packard is a company organization based out in Palo Alto, California, United States. It is known for research contribution in the topics: Signal & Substrate (printing). The organization has 34663 authors who have published 59808 publications receiving 1467218 citations. The organization is also known as: Hewlett Packard & Hewlett-Packard Company.


Papers
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Proceedings Article
17 Jun 2007
TL;DR: This work performed a set of experiments in a thermally isolated portion of a real data center, and validated that the potential savings is substantial and therefore warrants further work in this area to exploit the savings opportunity.
Abstract: Data center costs for computer power and cooling are staggering. Because certain physical locations inside the data center are more efficient to cool than others, this suggests that allocating heavy computational workloads onto those servers that are in more efficient places might bring substantial savings. This simple idea raises two critical research questions that we address: (1) How should one measure and rank the cooling efficiency of different places in a data center? (2) How substantial is the savings? We performed a set of experiments in a thermally isolated portion of a real data center, and validated that the potential savings is substantial and therefore warrants further work in this area to exploit the savings opportunity.

213 citations

Journal ArticleDOI
TL;DR: In this paper, a high density of highly oriented, metal-catalyzed silicon nanowires on a patterned silicon substrate and bridging of them between two vertical silicon sidewalls, which can be developed into electrodes of an electronic device are reported.
Abstract: We report simultaneous lateral growth of a high density of highly oriented, metal-catalyzed silicon nanowires on a patterned silicon substrate and bridging of nanowires between two vertical silicon sidewalls, which can be developed into electrodes of an electronic device. After angled deposition of catalytic metal nanoparticles on one of two opposing vertical silicon surfaces, we used a metal-catalyzed chemical vapour deposition process to grow nanowires and eventually form mechanically robust 'nanobridges'. The growth and bridging of these nanowire arrays can be integrated with existing silicon processes. This method of connecting multiple nanowires between two electrodes offers the high surface-to-volume ratio needed for nanosensor applications.

213 citations

Proceedings Article
11 Sep 2001
TL;DR: A historical perspective on technologies for intraand interenterprise business processes is provided, the state of the art is reviewed, and some open research issues are exposed.
Abstract: Over the past decade, there has been a lot of work in developing middleware for integrating and automating enterprise business processes. Today, with the growth in e-commerce and the blurring of enterprise boundaries, there is renewed interest in business process coordination, especially for inter-organizational processes. This paper provides a historical perspective on technologies for intraand interenterprise business processes , reviews the state of the art, and exposes some open research issues. We include a discussion of process-based coordination and event/rule-based coordination, and corresponding products and standards activities. We provide an overview of the rather extensive work that has been done on advanced transaction models for business processes, and of the fledgling area of business process intelligence.

213 citations

Proceedings ArticleDOI
24 Jun 2002
TL;DR: For the first time, nondimensional parameters are formulated to evaluate the thermal design and performance of large-scale data centers and will not only provide an invaluable tool to understand convective heat transfer in large data centers but also suggest means to improve energy efficiency in data centers.
Abstract: Large-scale data centers (~20,000m 2 ) will be the major energy consumers of the next generation. The trend towards deployment of computer systems in large numbers, in very dense configurations in racks in a data center, has resulted in very high power densities at room level. Due to high heat loads (~3MWs) in an interconnected environment, data center design based on simple energy balance with zones, is inadequate. Energy consumption of data centers can be severely increased by inadequate air handling systems and rack layouts that allow the hot and cold air streams to mix. In this paper, for the first time, we formulate nondimensional parameters to evaluate the thermal design and performance of large-scale data centers. The parameters, based on temperature and flow data, reflect the convective heat transfer and fluid flow inside the data center. These parameters have been formulated as indices that are scalable from rack level to data center level. To provide a proof of concept, computational fluid dynamic models of data centers are used to validate and demonstrate these indices. A first level design of experiment study is carried out to understand the effect of geometry and data center workload on the parameters. Different data center configurations are also investigated to understand the effectiveness of these parameters in specific cases. These parameters will not only provide an invaluable tool to understand convective heat transfer in large data centers but also suggest means to improve energy efficiency in data centers. Motivation

213 citations

Proceedings ArticleDOI
07 Nov 2011
TL;DR: It is found that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanose Cond scalePower-Gating a better fit for caches closer to main memory.
Abstract: This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.

213 citations


Authors

Showing all 34676 results

NameH-indexPapersCitations
Andrew White1491494113874
Stephen R. Forrest1481041111816
Rafi Ahmed14663393190
Leonidas J. Guibas12469179200
Chenming Hu119129657264
Robert E. Tarjan11440067305
Hong-Jiang Zhang11246149068
Ching-Ping Wong106112842835
Guillermo Sapiro10466770128
James R. Heath10342558548
Arun Majumdar10245952464
Luca Benini101145347862
R. Stanley Williams10060546448
David M. Blei98378111547
Wei-Ying Ma9746440914
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20231
202223
2021240
20201,028
20191,269
2018964