Showing papers by "INESC-ID published in 2001"

Rule based fuzzy cognitive maps - expressing time in qualitative system dynamics

Abstract: Time is essential in the study of system dynamics. When representing and analyzing the dynamics of complex quantitative systems, the problem of expressing the "effect" of time flow is naturally solved since the mathematical equations that describe the relations between the entities of the system are a function of time. However, if we are dealing with real world qualitative systems that are impossible or difficult to model using mathematical equations, then the use of natural language becomes the best tool to represent the system and expressing time influence becomes a real issue that has not been addressed before. This paper introduces a coherent procedure to implicitly represent time in rule based fuzzy cognitive maps which are a previously introduced methodology and tool to represent and simulate the dynamics of qualitative systems.

EC/NSF workshop on universal accessibility of ubiquitous computing: providing for the elderly event report

Abstract: The workshop took place on Alcacer do Sal, Portugal from May 22nd to May 25th, 2001 with the purpose to discuss approaches to universal usability for the elderly constituency Elderly citizens are a growing age group within developed countries and their needs have been mostly ignored by Information Technology and Computing as a whole The surge of mobile communications and universal access materialized in the push for UMTS in Europe provided a strong leitmotif for this meeting For the better part of a week, a group joining twenty-six people from several different communities gathered to discuss strategic issues arising from the new context The aim is to provide strategic inputs for major research programs in EU, USA and Japan The present document contains a summary account of the proceedings

Papous: The Virtual Storyteller

Abstract: This paper describes the development of Papous, a Virtual Storyteller. Our ultimate goal is to obtain a synthetic character that tells stories in an expressive and believable way, just as a real human storyteller would do. In this paper we describe the first version of Papous, our virtual storyteller. Papous can be seen as a virtual narrator who reads a text enriched with control tags. These tags allow the storywriter to script the behaviour of Papous. There are four types of tags: behaviour tags, where a specific action or gesture is scripted; scene tags, that allows for Papous to change the scene where he tells the story; illumination tags, to allow a new illumination pattern of the scene; and emotion tags, to change the emotional state of Papous. The texts, enriched with these tags, are then processed by Papous' different modules, which contain an affective speech module and an affective body expression module. In this paper we will provide details of the speech, gestures and environment control actions taken by each of the modules of Papous architecture.

Transducer composition for "on-the-fly" lexicon and language model integration

Abstract: We present the use of a specialized composition algorithm that allows the generation of a determinized search network for ASR in a single step. The algorithm is exact in the sense that the result is determinized when the lexicon and the language model are represented as determinized transducers. The composition and determinization are performed simultaneously, which is of great importance for "on-the-fly" operation. The algorithm pushes the language model weights towards the initial state of the network. Our results show that it is advantageous to use the maximum amount of information as early as possible in the decoding procedure.

Comparison of contention aware list scheduling heuristics for cluster computing

Abstract: In the area of static scheduling, list scheduling is one of the most common heuristics for the temporal and spatial assignment of a Directed Acyclic Graph (DAG) to a target machine. As most heuristics, list scheduling assumes fully connected homogeneous processors and ignores contention on the inter communication links. This article extends the list scheduling heuristic for contention aware scheduling on heterogenous arbitrary machines. The extension is based on the idea of scheduling edges to links, likewise the scheduling of nodes to processors. Based on this extension, we compare eight priority schemes for the node order determination of the first phase of list scheduling. Random graphs are generated and scheduled with the different schemes to homogenous and heterogenous parallel systems from the area of cluster computing. The experiments demonstrate the appropriateness of our extended list scheduling for homogeneous and heterogenous cluster architectures.

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level

Abstract: The purpose of this paper is to introduce a new RTL testability metric, IFMB, that evaluates the exercise of Implicit Functionality (IF) of operators and Multiple Branch (AM) coverage of conditional constructs. Although physical Defect Coverage (DC) strongly depends on the logic structure, thus preventing accurate DC estimation, RTL fault models can be derived, targeting high correlation between RTL fault coverage and DC. Using this evaluation criterion, previous RTL coverage metrics are compared with new metric. Due to its excellent correlation to DC, IFMB allows, at RT-level, test pattern quality evaluation aiming its reuse as production or lifetime test, using BIST. A methodology for testability analysis with the proposed RTL fault models is also presented, based on fast fault simulation using random patterns. Simulation based testability analysis errors are quantified Examples are presented where the proposed testability metrics are used to guide the inclusion of BIST in modules of ITC'99 benchmark circuits.

ICA of linear and nonlinear mixtures based on mutual information

Abstract: In independent component analysis (ICA), both linear and nonlinear, one of the best objective functions is the mutual information (MI) of the estimated components. However, use of the MI demands the estimation of the probability densities of those components from a finite number of training samples. Several forms of smoothing have been used to estimate these densities from data, including series expansions and Gaussian kernels. This paper proposes a new way to estimate these densities, simultaneously with the ICA operation. The resulting system is a neural network with a specialized architecture, optimized by a single objective function - the output entropy. The paper includes experimental results, which also illustrate that it is possible to perform nonlinear blind source separation when the mixtures have smooth nonlinearities.

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation

Abstract: A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture presents minimum latency, maximum throughput and full utilization of the hardware resources, combining both pipelining and parallel processing techniques. The implementation of an array processor for motion estimation in a single-chip using 0.25 µm CMOS technology is presented. Experimental results show that this processor is able to estimate motion vectors in 4CIF video sequences at a rate of 16 frames/s.

Comparative study of encoders for parallel-type adcs

Abstract: Analog-to-digital converters (ADCs) for high sampling frequencies have parallel-type architectures, where the output of the comparators is the so-called "thermometer code". The digital part of such ADCs can be just an encoder from the thermometer code to binary code; however, different types of error correction can be implemented to enhance the ADC overall performance. In this paper we compare three different types of encoders: without error correction; with 1 st order error correction; with n th order error correction. These encoders are compared with respect to the yield of the ADC with the different encoders, assuming the use of an identical analog part. The yield is defined by four different criteria: monotonicity, absence of missing codes, and either integral or differential nonlinearity below a specified value.

RTL design validation, DFT and test pattern generation for high defects coverage

Abstract: The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability Metrics, two approaches are combined: RTL DFT and TPG. RTL Design for Testability is illustrated through TPI (Test Point Insertion). RTL Test Pattern Generation is performed using the property that strong correlation exists between n-detection of RT-level faults and single detection of physical defects. The derived functional test leads to high Defects Coverage, DC, when the RTL description is synthesized into a physical layout. The proposed methodology enables tradeoff analysis, for different DFT solutions, or test pattern sequences. The resulting test patterns are, in fact, loosely deterministic patterns, suitable for low-cost BIST implementation. The usefulness of the methodology is ascertained using the mixed-level VeriDOS fault simulation tool and modules from the CMUDSP and TORCH ITC '99 benchmark circuits.

The development of a portuguese version of a media watch system.

Abstract: This paper summarizes the work that has been done concerning the Portuguese language in the scope of the ALERT project during its first year. The media watch system that is the goal of this project comprises many different modules, some of them common among the three languages of the project. This paper concentrates on the definition and collection of the necessary linguistic resources for Portuguese, and the development of the speech recognition, topic and jingle detection modules. The first version of the ALERT demo for European Portuguese is also described.

Parameterizable hardware architectures for automatic synthesis of motion estimation processors

Abstract: A new class of fully parameterizable multiple array architectures for motion estimation (ME) in video sequences based on the full search block matching (FSBM) algorithm is proposed in this paper. This class is based on a new and efficient AB2 single array architecture with minimum latency, maximum throughput and full utilization of the hardware resources. It provides the ability to configure the target processors according to the setup parameters, the processing time and the circuit area specified limits. With this purpose, a software configuration tool has been implemented to determine the set of possible configurations which fulfill the requisites of the video coder, providing the ability to automatically generate the VHDL description of the selected configuration. The implementation of a single array processor configuration on a single-chip is presented. Experimental results evidence the ability to estimate motion vectors in real-time with this configuration.

An introduction to a nonlinear programming approach to optimal continuous robust parametric H 2 control

Abstract: A parametric H 2 optimal control problem for linear continuous time-invariant systems is discussed. The control setup allows that any matrix coefficient of a system state space description be subjected to parameter uncertainties. Controllers with any order and any structure can be synthesized by recasting it as a Static Output Feedback problem. A modified H 2 cost functional that allows to start the optimization with a non stabilizing controller is used. First and second order derivatives for the modified H 2 cost functional with respect to system uncertainties and controller parameters are given. Based on this setup, several parametric robust design problems are formulated.

Adaptive regulation of an highly uncertain process: ARC welding temperature

Abstract: This paper concerns the application of adaptive predictive control for regulating arc welding trailing centerline temperature. Parallel integral action is used for achieving zero steady-state tracking error. As shown by experimental results, the process presents an high level of uncertainty, being impossible to stabilise all possible plant dynamics outcomes with a single linear, time i. ii van™ ant, controller. For tackling the high level of uncertainty in the process the MUSMAR adaptive algorithm, relying on separate estimation of predictive models is used. Experimental results are presented, forming the core of the paper. The possible convergence points of the adaptive controller together with the parallel integral action are characterized through the ODE method for the analysis of stochastic algorithms together with singular perturbation analysis.

Power Optimized Viterbi Decoder Implementation through Architectural Transforms

Abstract: Viterbi is an algorithm for error correction in the transmission of messages. It requires coding and decoding stages in the sender and receiver, respectively. These type of algorithms are very useful for the transmission of a type of messages where some degree of error in the received message is acceptable, such as, voice and video. The coding allows some error detection and correction. In this paper we present an architecture for the Viterbi Decoder. Using this initial structure, we have applied a set of transformation techniques aiming for a power optimized implementation. These techniques include pipelining, operation reduction/substitution and the reduction of transition activity. We show that it is possible to reduce the circuit's power consumption by more than half without impacting excessively on the area.