INESC-ID

About: INESC-ID is a nonprofit organization based out in Lisbon, Portugal. It is known for research contribution in the topics: Field-programmable gate array & Control theory. The organization has 932 authors who have published 2618 publications receiving 37658 citations.

Extension Variables in QBF Resolution.

Abstract: We investigate two QBF resolution systems that use extension variables: weak extended Q-resolution, where the extension variables are quantified at the innermost level, and extended Q-resolution, where the extension variables can be placed inside the quantifier prefix. These systems have been considered previously by (Jussila et al. 2007), who give experimental evidence that extended Q-resolution is stronger than weak extended Q-resolution. Here we prove an exponential separation between the two systems, thereby confirming the conjecture of (Jussila et al. 2007). Conceptually, this separation relies on showing strategy extraction for weak extended Q-resolution by boundeddepth circuits. In contrast, we show that this strong strategy extraction result fails in extended Q-resolution.

Advantages and GPU implementation of high-performance indexed DNA search based on suffix arrays

Abstract: A comparative analysis of high-performance implementations of two state of the art index structures that are of particular interest in the field of bioinformatics applications to accelerate the alignment of DNA sequences is presented. The two indexes are based on suffix trees and suffix arrays and were implemented in two different platforms: a quad-core CPU and a NVIDIA GeForce GTX 580 GPU, based on the newest Fermi architecture. Unlike what happens in conventional CPU implementations, the obtained experimental results reveal that GPU implementations clearly favor the suffix arrays, due to the achieved performance in terms of memory accesses. When compared with the CPU, the results demonstrate the possibility to achieve speedups as high as 85 when using the suffix array in the GPU, thus making it an adequate choice for high-performance bioin-fomatics applications.

Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test

Abstract: Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-V/sub DD/ test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering V/sub DD/ on the propagation delay time, while keeping invariant the observation pace at speed test, is similar to the effect of decreasing the clock period t/sub CLK/ while keeping nominal V/sub DD/. In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, /spl Delta//sub pd/ on depleted V/sub DD/ (i.e., on /spl Delta/V/sub DD/) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or V/sub DD/ decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower V/sub DD/) are used for delay fault detection and defect diagnosis. Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, is used to demonstrate the results.

Generating Worst-Case Stimuli for Accurate Power Grid Analysis

Abstract: Power distribution systems provide the voltages and currents that devices in a circuit need to operate properly and silicon success requires its careful design and verification. However, problems like voltage drop, ground bounce and electromigration, which may cause chip failures, are worsening, as more devices, operating at higher frequencies, are placed closer together. Verification of this type of systems is usually done by simulation, a costly endeavor given the size of current grids, making the determination of the worst-case input setting a crucial task. Current methodologies are based on supposedly safe settings targeting either unrealistic simultaneous switching on all signals or heuristic accounts of the joint switching probability of nearby signals. In this paper we propose a methodology for computation of the worst-case stimuli for power grid analysis. This is accomplished by determining the input vector that maximizes the number of gates, in close proximity to each other, that can switch in a given time window. The addition of these temporal and spatial restrictions makes the solution of the underlying optimization problem feasible. Comparisons with existing alternatives show that only a fraction of the gates change in any given timing window, leading to a more robust and efficient verification methodology.

A framework to support multiple reconfiguration strategies

Abstract: Self-management is a key feature of autonomic systems. This often demands the dynamic reconfiguration of a distributed application. An important issue in the reconfiguration process is the strategy that is used to coordinate the multiple participants involved in the reconfiguration. This paper addresses the problem of providing support for multiple reconfiguration strategies in autonomic systems that are designed as self-reconfigurable service compositions. We decompose existing strategies in two separate aspects -- an orchestration protocol and a local reconfiguration procedure. This separation allowed us to design a set of generic pluggable components that can be integrated in concrete service compositions, in order to support different strategies. The strategy selection is performed according to the semantics of each reconfiguration. To illustrate our approach, we have implemented an instance of these pluggable components for the RAppia composition framework.