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Institution

INESC-ID

NonprofitLisbon, Portugal
About: INESC-ID is a nonprofit organization based out in Lisbon, Portugal. It is known for research contribution in the topics: Field-programmable gate array & Control theory. The organization has 932 authors who have published 2618 publications receiving 37658 citations.


Papers
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01 Jan 2010
TL;DR: The phonotactic VID system, based on Phone Recognition and Language Modelling, focuses on a single tokenizer that combines distinctive knowledge about differences between the target varieties to improve results by up to 13% compared to a standard variety baseline.
Abstract: This paper presents a new approach of building a language identification system using a specialized Phone Recognition system followed by Language Modeling (PRLM) to differentiate Portuguese varieties spoken in African Countries from European Portuguese. The system is designed to focus on exploiting the phonotactic information of a single discriminatively trained tokenizer for the specific pair of target varieties. In contrast to other PRLM-based methods, the single tokenizer already combines distinctive knowledge about the differences between both target varieties. This knowledge is introduced into a dedicated multiple-stream Multi-Layer Perceptron (MLP) phone recognizer by training mono-phoneme models for two varieties as contrasting phoneme-like classes within a single tokenizer. Significant improvements in terms of identification rate and computational cost were achieved compared to a conventional single tokenizer PRLM-based systems and to the combination of up to five parallel PRLM identifiers. The method is also applied to other varieties of Portuguese yielding similar results. Variety identification; Portuguese varieties

11 citations

Proceedings ArticleDOI
12 Nov 2007
TL;DR: This paper presents a novel design approach to customize the routers in a network-on-chip for reconfigurable systems, and indicates that the proposed algorithm can provide significantly better solutions compared to the uniform router design, which is typically used.
Abstract: A fundamental objective in the design of a network-on-chip is to minimize its area and power consumption while keeping the performance requirements at acceptable levels. The trade-offs involved in the process depend on the target technology, ASIC or FPGA. This paper presents a novel design approach to customize the routers in a network-on-chip for reconfigurable systems. More specifically, given a topology and the traffic requirements, the design process automatically finds the architecture of each router, adjusting the size of the buffers and the configuration of the switch matrix, such that the overall area and performance are maximized. The results indicate that the proposed algorithm can provide significantly better solutions compared to the uniform router design, which is typically used.

11 citations

01 Jan 2006
TL;DR: An architecture to realize an RF quadrature oscillator, in which a frequency generated by a Direct Digital Synthesis (DDS) system is added to (or subtracted from) the frequencygenerated by a Phase-Locked Loop (PLL).
Abstract: We propose an architecture to realize an RF quadrature oscillator, in which a frequency generated by a Direct Digital Synthesis (DDS) system is added to (or subtracted from) the frequency generated by a Phase-Locked Loop (PLL). The DDS system is easily reconfigurable to change the channel spacing and bandwidth, and allows the implementation of several digital modulation schemes. A computer program was developed to calculate the parameters of the DDS system, based on the specifications supplied by the user, and to generate the VHDL code of the digital part of the system. The DDS is designed to obtain outputs in quadrature with a minimum ROM area. The DDS is implemented in a FPGA and has excellent quadrature relation throughout the frequency band of the system.

11 citations

Journal ArticleDOI
TL;DR: In this paper, a mathematical model that simulates the operation of a solid-state bipolar Marx modulator topology, including the influence of parasitic capacitances, is presented and discussed as a tool to analyze the circuit behavior and to assist the design engineer to select the semiconductor components and to enhance the operating performance.
Abstract: A mathematical model that simulates the operation of a solid-state bipolar Marx modulator topology, including the influence of parasitic capacitances is presented and discussed as a tool to analyze the circuit behavior and to assist the design engineer to select the semiconductor components and to enhance the operating performance. Simulations show good agreement with experimental results, considering a four stage circuit assembled with 1200 V isolated gate bipolar transistors and diodes, operating at 1000 V dc input voltage and 1-kHz frequency, giving 4 kV and 10-μs output pulses into several resistive loads. Results show that parasitic capacitances between Marx cells to ground can significantly load the solid-state switches, adding new operating circuit conditions.

11 citations

Journal ArticleDOI
TL;DR: This work introduces a scheme, which is called the leading-term Monte Carlo regression, which seeks to remove bias by replacing a ’cloud’ of Monte Carlo estimates—carried out at different discretization levels—for the usual single Monte Carlo estimate.
Abstract: The numerical approximation of boundary value problems by means of a probabilistic representations often has the drawback that the Monte Carlo estimate of the solution is substantially biased due to the presence of the domain boundary. We introduce a scheme, which we have called the leading-term Monte Carlo regression, which seeks to remove that bias by replacing a 'cloud' of Monte Carlo estimates--carried out at different discretization levels--for the usual single Monte Carlo estimate. The practical result of our scheme is an acceleration of the Monte Carlo method. Theoretical analysis of the proposed scheme, confirmed by numerical experiments, shows that the achieved speedup can be well over 100.

11 citations


Authors

Showing all 967 results

NameH-indexPapersCitations
João Carvalho126127877017
Jaime G. Carbonell7249631267
Chris Dyer7124032739
Joao P. S. Catalao68103919348
Muhammad Bilal6372014720
Alan W. Black6141319215
João Paulo Teixeira6063619663
Bhiksha Raj5135913064
Joao Marques-Silva482899374
Paulo Flores483217617
Ana Paiva474729626
Miadreza Shafie-khah474508086
Susana Cardoso444007068
Mark J. Bentum422268347
Joaquim Jorge412906366
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202311
202252
202196
2020131
2019133
2018126