INESC-ID

About: INESC-ID is a nonprofit organization based out in Lisbon, Portugal. It is known for research contribution in the topics: Computer science & Context (language use). The organization has 932 authors who have published 2618 publications receiving 37658 citations.

Scalable and high throughput biosensing platform

Abstract: A novel multi-channel high performance embedded system capable of high throughput biological analysis is proposed in this paper. Despite other integrated lab-on-chip solutions based on magnetoresistive biochips have already been developed, they lack the scalability and computational resources to cope with new biochip designs featuring more than 1000 sensors. A new configurable acquisition and processing architecture is proposed, combining dedicated coprocessors to perform signal filtering and other computational demanding tasks, with a central processor controlling the whole system. The mapping of the architecture into a Zynq SoC demonstrated its ability to support 8 times more sensors, while ensuring a sampling frequency 1000+ times higher than the previous platforms. Furthermore, the Zynq reconfiguration abilities provide a mechanism to adapt the processing and maximize the biological sensitivity.

A Reconfigurable Quadrature Oscillator Based on a Direct Digital Synthesis System

Abstract: We propose an architecture to realize an RF quadrature oscillator, in which a frequency generated by a Direct Digital Synthesis (DDS) system is added to (or subtracted from) the frequency generated by a Phase-Locked Loop (PLL). The DDS system is easily reconfigurable to change the channel spacing and bandwidth, and allows the implementation of several digital modulation schemes. A computer program was developed to calculate the parameters of the DDS system, based on the specifications supplied by the user, and to generate the VHDL code of the digital part of the system. The DDS is designed to obtain outputs in quadrature with a minimum ROM area. The DDS is implemented in a FPGA and has excellent quadrature relation throughout the frequency band of the system.

A New Real Time Lyapunov Based Controller for Power Quality Improvement in Unified Power Flow Controllers Using Direct Matrix Converters

Abstract: This paper proposes a Direct Matrix Converter operating as a Unified Power Flow Controller (DMC-UPFC) with an advanced control method for UPFC, based on the Lyapunov direct method, presenting good results in power quality assessment. This control method is used for real-time calculation of the appropriate matrix switching state, determining which switching state should be applied in the following sampling period. The control strategy takes into account active and reactive power flow references to choose the vector converter closest to the optimum. Theoretical principles for this new real-time vector modulation and control applied to the DMC-UPFC with input filter are established. The method needs DMC-UPFC dynamic equations to be solved just once in each control cycle, to find the required optimum vector, in contrast to similar control methods that need 27 vector estimations per control cycle. The designed controller’s performance was evaluated using Matlab/Simulink software. Controllers were also implemented using a digital signal processing (DSP) system and matrix hardware. Simulation and experimental results show decoupled transmission line active (P) and reactive (Q) power control with zero theoretical error tracking and fast response. Output currents and voltages show small ripple and low harmonic content.

Reusing a time ontology

Abstract: Ontologies are becoming crucial in several disparate areas, such as the Semantic Web or Knowledge Management. Ontology building is still more of an art than an engineering task. None of the available methodologies to build ontologies from scratch has been widely accepted. One cost effective way of building ontologies is by means of reuse. In this article we describe the development of an ontology of Time by means of reuse, following an evolving prototyping life cycle. This process involved several complex subprocesses: knowledge acquisition and requirement specification using Natural Language techniques, reverse engineering, knowledge representation translation, technical evaluation. As far as we know, this is the first time that all these processes have been combined together. We describe the techniques and best practices that were successfully used.

Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems

Abstract: The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication channel(s) is (are) faulty. This is not trivial in GALS systems, for which the CDC issue is challenging. The underlying principle of the proposed methodology is to embed a CDC test and diagnosis (CDC T&D) structure in each locally synchronous domain. Complete device-to-device communication channels are tested, including transceivers, buses, and board connectors. Identical test patterns (generated to detect static (stuck-at, shorts and open faults) and dynamic (crosstalk) faults) are used in each FPGA. The proposed CDC T&D methodology is validated in a case study, the acquisition electronics of a complex multi-board, multibus, multi-FPGA (nine Xilinx™ xc2v4000–4bf957) system. Test and validation results are presented.