INESC-ID

About: INESC-ID is a nonprofit organization based out in Lisbon, Portugal. It is known for research contribution in the topics: Field-programmable gate array & Control theory. The organization has 932 authors who have published 2618 publications receiving 37658 citations.

Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations

Abstract: A new moduli set {2n-1, 2n+3, 2n+1, 2n-3} has recently been proposed to represent numbers in Residue Number Systems (RNS), increasing the number of channels. With this, the processing time can be reduced by simultaneously exploiting the carry-free characteristic of the modular arithmetic and improving the parallelism. In this paper, hardware structures for addition and multiplication operation in RNS for the moduli {2n-3} and {2n+3} are proposed and analyzed. In order to evaluate the performance of the proposed units they were implemented on an ASIC technology. The obtained experimental results suggest that the performance of the moduli {2n\pm3} are acceptable but demand more area resource and impose a larger delay than the typically used {2n\pm1} arithmetic units. Addition units require at least 42\% more area for a performance identical to the {2n+1} modulo adder. The multiplication units require up to 37% more area and impose a delay 25% higher. This paper also suggests that more balanced moduli sets should be developed in order to achieve more efficient RNS.

Polygon Detection from a Set of Lines

Abstract: Detecting polygons defined by a set of line segments in a plane is an important step in the analysis of vectorial drawings. This paper presents an approach that combines several algorithms to detect basic polygons from a set of arbitrary line segments. The resulting algorithm runs in polynomial time and space, with complexities of O((N +M)) and O((N +M)) respectively, where N is the number of line segments and M is the number of intersections between line segments. Our choice of algorithms was made to strike a good compromise between efficiency and ease of implementation. The result is a simple and efficient solution to detect polygons from lines.

High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies

Abstract: In this paper, high voltage (HV) tolerant level-shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level-shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to ensure a specific behavior during out of the normal mode periods (power up; power down; reset; etc.). These high voltage tolerant logic circuits were used in the power block of buck converter designed in a standard 3.3 V, 0.13 mum CMOS process, powered by an input voltage range from 2.7 V to 4.2 V.

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops

Abstract: Many video and image/signal processing applications can be structured as sequences of data-dependent tasks using a consumer/producer communication paradigm and are therefore amenable to pipelined execution. This paper presents an execution technique to speed-up the overall execution of successive, data-dependent tasks on a reconfigurable architecture. The technique pipelines sequences of data-dependent tasks by overlapping their execution subject to data-dependences. It decouples the concurrent data-path and control units and uses a custom, application data-driven, fine-grained synchronization and buffering scheme. In addition, the execution scheme allows for out-of- order, but data-dependent producer-consumer pairs not allowed by previous data-driven pipelining approaches. The approach has been exploited in the context of a high-level compiler targeting FPGAs. The preliminary experimental results reveal noticeable performance improvements and buffer size reductions for a number of benchmarks over traditional approaches.

Sentiment Analysis and Topic Classification based on Binary Maximum Entropy Classifiers

Abstract: This work was partially supported by national funds through FCT – Fundacao para a Ciencia e Tecnologia, under project PEst-OE/EEI/LA0021/2011, and by DCTI – ISCTEIUL – Lisbon University Institute.