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Showing papers by "Mitsubishi Electric published in 1995"


PatentDOI
TL;DR: A system for the control from a distance of machines having displays incls hand gesture detection in which the hand gesture causes movement of an on-screen hand icon over anon-screen machine control icon, with the hand icon moving the machine control icons in accordance with sensed hand movements to effectuate machine control.

838 citations


Patent
27 Dec 1995
TL;DR: In this article, a system located in an automobile provides personalized traffic information and route planning capabilities using equipment which is becoming standard in automobiles, such as on-board navigation systems and cellular telephones.
Abstract: A system located in an automobile provides personalized traffic informationnd route planning capabilities. This system uses equipment which is becoming standard in automobiles, such as on-board navigation systems and cellular telephones. On-board navigation systems use global positioning system (GPS) satellites to position the automobile with respect to streets in a map database. As the automobile moves, the navigation system updates the location. A central database includes travel time information for each street segment and transition between street segments in the map database. Based upon the travel time information in the database, a route from a current location to a desired destination, or series of destinations, can be planned in order to have a minimum travel time. The route can be provided to the on-board navigation system, which then directs the driver in traveling the route. The cellular telephone in the automobile can be used for communicating with the central database to obtain travel times for route planning. In order to provide dynamic travel time information to the central database, each automobile in the system operates as a data collector. As various street segments are traversed, the travel time for each segment is recorded. The travel time and street segment information is periodically transferred to the central database through the cellular telephone connection. The central database then combines the travel time data from each automobile to create accurate travel time data for each street segment.

304 citations


Patent
05 Apr 1995
TL;DR: In this paper, a system for safely updating a file with the risk of losing work performed at one site due to work performed on the file at another site uses a journal or log at each site which is updated after a file is modified.
Abstract: In a distributed file environment, a system for safely updating a file wiut risk of losing work performed at one site due to work performed on the file at another site uses a journal or log at each site which is updated after a file is modified. This log is compared with the logs from other sites before a file is used at any one site, so that new versions can be propogated automatically and safely to out-of-date sites, with the user immediately alerted if conflicting versions of the file exist at different sites. The reconciliation can be applied to collections of files, automatically updating only those files for which it is safe to and necessary do so. Since reconciliation occurs at times selected by the user, inconsistent or partially completed versions of files need not be propogated to other sites. Additionally, logs may be built incrementally by occasionally observing the state of the systems in terms of the files and their time stamps and creating additional log entries reflecting appearance, disappearance and changes of files. Furthermore, logs may be purged of obsolete entries by including additional log entries indicating the most recent time each site has participated in a reconciliation and deleting obsolete entries that all sites have seen.

275 citations


Patent
03 May 1995
TL;DR: In this article, a hand-held accelerometer-based computer control device is used to control on-screen animated characters presented by a computer-driven display in which the movement, persona, or style of the character is controlled through movement of the device in a predetermined pattern which results in recognizable patterns of accelerations that are detected to give the onscreen character a particular persona or style determined by the user.
Abstract: A compact convenient hand-held, accelerometer-based computer control devices utilized to control on-screen animated characters presented by a computer-driven display in which the movement, persona, or style of the character is controlled through movement of the device in a predetermined pattern which results in recognizable patterns of accelerations that are detected to give the on-screen character a particular persona or style determined by the user. Thus, the system requires only a series of easily learned hand movement patterns for corresponding character control. In an alternative embodiment, once a movement has been determined, the style or emotional content of the movement is specified directly from gross accelerometer output without pattern matching. In another embodiment, the outputs of two or more accelerometers are combined, with the combined waveforms constituting a language for graphical object control. In a still further embodiment, one or more patterns are detected serially as a language to direct the appropriate movement or persona for the character or icon presented on-screen. In yet another embodiment, accelerations are normalized to the local gravitational field such that the orientation of the control device is irrelevant. In an additional embodiment, since the location of the on-screen character is known, the character may be given incremental motions from this location by moving the device in the direction of the intended incremental motion, thus to direct the motion of the character in the same direction as the hand movement.

224 citations


Patent
31 Jan 1995
TL;DR: In this paper, a synchronous memory array is divided into a plurality of small memory arrays, and each array is connected to the corresponding global I/O line pair through the local I/Os line pair.
Abstract: In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

148 citations


Patent
31 Jan 1995
TL;DR: In this paper, the voxel-based objects are manipulated and interacted with in a physically ristic way such that collisions are automatically detected and the graphical objects are prevented from penetrating each other.
Abstract: Voxel-based objects are manipulated and interacted with in a physically ristic way such that during movement of the graphical objects, collisions are automatically detected and the graphical objects are prevented from penetrating each other. Applications include computer graphics and animation, CAD/CAM, and virtual reality applications that require real-time interaction between complex three-dimensional object models. When objects are represented in a voxel-based format where objects consist of clusters of regularly or irregularly spaced sampled data points, rather than a conventional graphic format where objects are represented by lists of polygons, primitive surfaces, or geometries, moving objects in virtual space involves shifting the voxel-based data in a large memory array representing the virtual space of the system and detecting collisions among moving objects by checking the new memory locations of object voxels to see if they are already occupied.

122 citations


Patent
25 Apr 1995
TL;DR: In this paper, a highly efficient and compact ozone generating apparatus was provided, in which a very short air gap of about 0.2 mm was formed at high accuracy, and an elastic body was mounted on the back face of an electrode, thereby enhancing an air gap accuracy of the discharge space.
Abstract: There is provided a highly efficient and compact ozone generating apparatus in which a very short air gap of about 0.2 mm is formed at high accuracy. Non-discharge portions are dispersed and disposed to cover an entire discharge space, or a spacer is provided to form the non-discharge portion. Further, an elastic body is mounted on a back face of an electrode, thereby enhancing an air gap accuracy of the discharge space.

91 citations


Proceedings ArticleDOI
06 Jun 1995
TL;DR: In this paper, an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention was carried out for full DRAM operation and a proposal was made to obtain superior dynamic data retraction time.
Abstract: SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.

91 citations


Patent
20 Dec 1995
TL;DR: In this paper, a reset signal generating circuit is provided to reset the internal circuits when the power supply voltage rises to reach a predetermined operating voltage and when it is lowered below a minimum voltage of voltages.
Abstract: In a non contact IC card for generating a power supply voltage from electric waves transmitted via wireless communication from a base unit, a reset signal generating circuit is provided to reset the internal circuits when the power supply voltage rises to reach a predetermined operating voltage and when it is lowered below a minimum voltage of voltages which ensure the normal operation of the internal circuits, thereby operations such as a writing operation in the internal circuits can be made stable and the time required for communication can be shortened.

67 citations


Journal ArticleDOI
15 Feb 1995
TL;DR: A half-pel precision MPEG2 motion estimation processor using a 0.5 /spl mu/m CMOS technology supports all prediction modes in MPEG2 including frame, field and dual-prime prediction, and estimates three vectors concurrently.
Abstract: A half-pel precision MPEG2 motion estimation processor using a 0.5 /spl mu/m CMOS technology supports all prediction modes in MPEG2 including frame, field and dual-prime prediction, and estimates three vectors concurrently. The multiple processor configuration allows a search range expansion by /spl plusmn/127.5, keeping bus traffic constant. It integrates 850 K transistors in a 13.85 mm/spl times/13.55 mm silicon die. The observed maximum operating frequency is 75 MHz. At 40 MHz for NTSC, the peak computational power is 20 GOPS and the power dissipation is 1.9 W.

61 citations


Patent
19 May 1995
TL;DR: In this article, a system for spelling correction in which the context of a wordn a sentence is utilized to determine which of several alternative or possible words was intended is provided, where the probability that a particular alternative was the word that was intended was determined through Bayesian analysis utilizing multiple kinds of features of the context, such as the presence of certain characteristic words within some distance of the target word, or the presence that certain characteristic patterns of words and part-of-speech tags around a target word.
Abstract: A system is provided for spelling correction in which the context of a wordn a sentence is utilized to determine which of several alternative or possible words was intended. The probability that a particular alternative was the word that was intended is determined through Bayesian analysis utilizing multiple kinds of features of the context of the target word, such as the presence of certain characteristic words within some distance of the target word, or the presence of certain characteristic patterns of words and part-of-speech tags around the target word. The system successfully combines multiple types of features via Bayesian analysis through means for resolving egregious interdependencies among features. The system first recognizes the interdependencies, and then resolves them by deleting all but the strongest feature involved in each interdependency, thereby allowing it to make its decisions based on the strongest non-conflicting set of features. In addition, the robustness of the system's decisions is enhanced by the pruning or deletion from consideration of certain features, in one case by deleting features for which there is insufficient evidence in the training corpus to support reliable decision-making, and secondly by deleting features which are uninformative at discriminating among the alternative spellings of the target word under consideration.

Patent
21 Jul 1995
TL;DR: In this paper, the addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of the flash memory devices, such that the address for the plurality of continuous logic blocks is respectively distributed into the plurality, and when block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two devices in which physical blocks to be erased exist.
Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

Patent
05 Jun 1995
TL;DR: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112), can be found in this article.
Abstract: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.

Patent
15 Jun 1995
TL;DR: In this paper, a single-chip microprocessor with a self-testing function for detecting internal errors or defects while mounted to a circuit board without adversely affecting any external electronic devices connected thereto is presented.
Abstract: A single-chip microprocessor with a self-testing function for quickly detecting internal errors or defects while mounted to a circuit board without adversely affecting any external electronic devices connected thereto. A single-chip microprocessor comprising a built-in self-testing function for testing the internal circuitry thereof comprises a test mode signal output means for outputting the test mode signal when in the test mode, which is a mode for self-diagnostic testing of the internal circuitry; and an external output holding means disposed to the external output means for outputting signals from an external output terminal, and holding the output signal status of the external output terminal while the test mode signal is input from the test mode signal output means; and testing the internal circuitry of the single-chip microprocessor while holding the output signal status of the external output terminal.

Patent
21 Jul 1995
TL;DR: A closed caption decoder with a pause function suitable for learning a language comprising: a closed caption decode circuit for decoding closed caption signals included in video signals outputted from a video cassette recorder and for outputting a detection signal when a predetermined control code is decoded; a timer which measures an elapse of time from a time when the control code was decoded.
Abstract: A closed caption decoder with a pause function suitable for learning a language comprising: a closed caption decode circuit for decoding closed caption signals included in video signals outputted from a video cassette recorder and for outputting a detection signal when a predetermined control code is decoded; a timer which measures an elapse of time from a time when the predetermined control code is decoded; and a pause control circuit for instructing the caption decode means to perform a pause operation of caption decode and the video cassette recorder to perform a pause of video reproduction when the detection signal is outputted form the closed caption decode circuit and for outputting a pause termination signal of caption decode to the closed caption decoder and a pause termination signal of video reproduction to the video cassette recorder when the timer measures a predetermined period of time

Patent
11 Jul 1995
TL;DR: In this article, a current control circuit of a ring oscillator is provided for use in PLL oscillators, which consists of a first circuit having a first current source and a first transistor connected in series.
Abstract: A current control circuit of a ring oscillator is provided for use in the PLL oscillators. A current control circuit used in the ring oscillator comprises a first circuit having a first current source and a first transistor connected in series; a second circuit connected with the first circuit in parallel and having n second constant current sources and n second transistors connected in series, respectively, the second transistors are current mirrored with the first transistor in the first circuit, respectively; a third circuit connected with the first circuit in parallel and having a third transistor and a fourth transistor connected in series, the fourth transistor is current mirrored with the first transistor; n diodes connected to a connecting point of said third transistor and the fourth transistor for supplying currents to connecting points of n second constant current sources and the second transistor, respectively; an input terminal connected with the connecting point of the first constant current source and the first transistor.

Journal ArticleDOI
TL;DR: A new adaptive repetition control system that can improve follow-up capability by applying repetition control theory to tracking control and which can change the learning capacity according to such nonperiodic components as insufficient stability margin, disk drive vibration and disk defects, in response to the degree of track correlation is developed.
Abstract: The advent of digital video disks (DVD) has lead to narrower tracks along with a demand for higher density in the field of optical disks. This general and recent trend requires the improvement of follow-up capability within limits which are not detrimental to stability and speed of response. We have developed a new adaptive repetition control system that can improve follow-up capability by applying repetition control theory to tracking control, and which can change the learning capacity according to such nonperiodic components as insufficient stability margin (one of the problems in repetition control), disk drive vibration and disk defects, in response to the degree of track correlation. Furthermore, the division of the learning portion into two stages, namely long-term and short-term storage memories, compensates for the short-term memory being degraded by insufficient correlation and enhance the learning capability when disturbance occurs. As a result we were able to reduce the track error by disk eccentricity down to 0.02 /spl mu/m or less in a DVD disk with an eccentricity similar to compact disks (CD), and can confirm that the disk functions in a stable fashion even with interference from irregular disturbances. >

Patent
11 Sep 1995
TL;DR: In this article, a real-time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM when accessing to an emROM which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.
Abstract: The microcomputer provides with surroundings where data in a RAM can be monitored on the outside without employing an external bus. When a command requesting accessing to a RAM is received from an external monitor, a real time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM. On the other hand, when accessing to an emROM, which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.

Patent
28 Aug 1995
TL;DR: In this paper, a system for virtual environments in which graphical objects are depicted in a space to achieve the required high accuracy regardless of location through establishing locales or subdivisions of the global coordinate system and establishing an origin for each locale, such that the specification of position and movement of a graphical object in the locale can be made with greater precision than using a global coordinates system, thus eliminating the need for high-precision floating point processors or emulation.
Abstract: A system for virtual environments in which graphical objects are depicted in a space to achieve the required high accuracy regardless of location through establishing locales or subdivisions of the global coordinate system and establishing an origin for each locale, such that the specification of position and movement of a graphical object in the locale can be made with greater precision than using a global coordinate system, thus eliminating the need for high-precision floating point processors or emulation. The system permits designers of virtual environments to work independently on their locales, with overlap being controlled through specifying distance between locale origins as well as relative orientation between the locales. The system also permits ignoring information from non-relevant distant locales to, minimize processing and network bandwidth requirements.

Patent
21 Nov 1995
TL;DR: In this paper, a computer program version update system reduces storage space usage and enables calling programs to invoke any version of a program using the same name by storing only modified modules of the program for different program versions.
Abstract: A computer program version update system reduces storage space usage and enables calling programs to invoke any version of a program using the same name by storing only modified modules of a program for different program versions. Multiple versions of a program can thus have the same name. Any version of the program may be constructed from the modules upon command with a user issuing such a command and including a version number corresponding to the requested version as a parameter to invoke a program construction procedure.

Patent
26 Sep 1995
TL;DR: In this paper, a buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.
Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied. A buffer circuit with driving current adjusting function of the present invention comprises a buffer circuit which is controlled by a control signal for supplying a most appropriate driving current to a load; a load detecting circuit for detecting a phase difference between an input signal and an output signal of the buffer circuit and for outputting voltage corresponding to the phase difference, a control signal generating circuit for generating a signal which controls the driving current of the buffer circuit in response to an output signal of the load detecting circuit, the control signal controls so that the driving current of buffer circuit is increased when delay time of buffer circuit becomes long and the driving current of buffer circuit is decreased when delay time becomes short.

Journal ArticleDOI
TL;DR: In this article, the strength characteristics of adhesive/rivet combined lap joints were investigated, and the results indicated that the fatigue strength of adhesive joints can be improved through combination with rivets of nearly equal or slightly higher fatigue strength than the adhesive joint.
Abstract: Adbesive/rivet combined bonding has attracted special interest recently as a joining technique of highstrength steel because of its high joint efficiency. In the present study, the strength characteristics of adhesive/rivet combined lap joints were investigated. To darify bonding conditions capable of improving the fatigue strength of combined joints, fatigue tests were conducted on the rivet, adhesive and adhesive/rivet combined joints with different lap widths, adhesive and rivet strengths. Furthermore, to compare fatigue crack initiation and propagation behavior of the adhesive joint with that of the combined joint, the strain changes were measured by strain gauges bonded onto the adherend plate near the lap end. The results indicate that the fatigue strength of adhesive joints can be improved through combination with rivets of nearly equal or slightly higher fatigue strength than the adhesive joint. Furthermore, we also confirmed that fatigue cracks propagate more gradually in combined joints...


Patent
05 Jun 1995
TL;DR: In this article, a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to an equal number of the second group simultaneously.
Abstract: According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

Patent
28 Jun 1995
TL;DR: In this article, a switching regulator is composed of digital circuits only, consisting of a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver.
Abstract: A switching regulator is composed of digital circuits only. A switching regulator (30) comprises a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver (2). An output terminal (Q) of an RS flip-flop (5) is connected to one input end of the OR gate (6), the output of a timer (40c) is applied to a set terminal (S) of the RS flip-flop (5), and the output of a comparator (4) is applied to a reset terminal (R1) through an OR gate (7). At a non-reverse input end of the comparator (4), a reference voltage (VE) is applied by a D/A convertor (40b), while a feedback voltage (VFB) is applied to a reverse input end. Accordingly, chopping of the switching transistor (1) is done on the basis of a rectangular pulse.

Proceedings ArticleDOI
01 May 1995
TL;DR: A new architectural mechanism, called predicating, is proposed, which provides unconstrained speculative execution, and significantly improves performane, and achieves a 2.45x speedup over scalar machines.
Abstract: Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achieve both a high instruction per cycle rate and high clock rate. Pure compiler-based approaches, however, have greatly limited instruction scheduling due to a limited ability to handle side effects of speculative execution. Significant performance improvement is, thus, difficult in non-numerical applications. This paper proposes a new architectural mechanism, called predicating, which provides unconstrained speculative execution. Predicating removes restrictions which limit the compiler's ability to schedule instructions. Through our hardware support, the compiler is allowed to move instructions past multiple basic block boundaries from any succeeding control path. Predicating buffers the side effects of speculative execution with its predicate, and the buffered predicate efficiently commits or squashes the side effects. The mechanism also provides a speculative exception handling scheme. The scheme, called the future condition, properly postpones speculative exceptions and efficiently restarts the process. We show that our mechanism can be implemented through a modest amount of hardware with little complexity. The evaluation results show that our mechanism significantly improves performance, and achieves a 2.45x speedup over scalar machines.

Journal ArticleDOI
TL;DR: In this paper, a digital EDM gap monitor has been developed to detect the time ratios of gap states with a resolution of 0.2 μs, and the effect of sensing parameter combinations on control aspects and performance of manual setting, integral control and adaptive integral control methods have been carried out.
Abstract: This paper reports a monitoring and adaptive integral control strategy for EDM to regulate the cycle time of the periodical retraction (jumping of the tool electrode according to the gap condition. A digital EDM gap monitor has been developed to detect the time ratios of gap states with a resolution of 0.2 μs. The theoretical and experimental analysis of the effect of sensing parameter combinations on control aspects and performance of manual setting, integral control and adaptive integral control methods have been carried out. Experimental verification shows that the proposed system results in higher erosion rate, better machining stability, and complete avoidance of are damage

Patent
14 Apr 1995
TL;DR: In this article, a packet processor has memory storing an internal free buffer list, which is loaded from an external buffer list memory, which contains a free buffer lists for each application.
Abstract: A network interface using per-application free buffer lists includes a pat processor which processes an incoming message and stores packet data into free buffers designated for the application for which the message intended. The packet processor has memory storing an internal free buffer list. The internal free buffer list is loaded from an external free buffer list memory, which contains a free buffer list for each application. Each time a message arrives for a given application, the packet processor retrieves a portion of the external free buffer list for the application and loads the portion into the internal free buffer list. The portion which is loaded is a number of free buffers which is thought to be sufficient to handle an anticipated size of the incoming message. As a packet is processed, data are deposited in the buffers specified in the internal list. Any internal buffers unused after the packet is processed are attached to the end of the list of filled buffers returned, providing a self-cleaning property that allows an application to exert some control over which buffer an incoming packet uses. If packet data remains after the internal free buffer list is used up, the packet processor retrieves another portion of the external free buffer list and continues processing the message. To facilitate reading only a portion of the external free buffer list, the list may be organized as a two-dimensional structure, such as a linked list of free buffer lists.

Patent
14 Jul 1995
TL;DR: In this paper, a non-contact type IC card includes a programmable memory divided into a user area for storing application data, and a system area with a system password and effective code indicating requirement of collation of the system password.
Abstract: A non-contact type IC card includes a programmable memory divided into a user area for storing application data, and a system area for storing a system password and a system password effective code indicating requirement of collation of the system password. If the system area of the memory includes the system password effective code, access to the system area by an external apparatus is permitted only when passwords are identical as a result of password collation. If the system area does not include the system password effective code, the access by the external apparatus can be permitted without the password collation.

Journal ArticleDOI
TL;DR: In this article, the soft error susceptibility of the local position and structure of DRAM to soft error induced by incident ions on reverse biased p-n junctions with barrier well structures has been clarified.
Abstract: Soft errors induced in a dynamic random access memory (DRAM) have been measured using a nuclear microprobe. Soft error susceptibility of the local position and structure to the soft error has been clarified. Collection efficiency of charge carriers, induced by incident ions on reverse biased p-n junctions with barrier well structures, has been verified for various implantation doses for well formation.