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Institution

Mitsubishi Electric

CompanyRatingen, Germany
About: Mitsubishi Electric is a company organization based out in Ratingen, Germany. It is known for research contribution in the topics: Signal & Voltage. The organization has 23024 authors who have published 27591 publications receiving 255671 citations. The organization is also known as: Mitsubishi Electric Corporation & Mitsubishi Denki K.K..


Papers
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Journal ArticleDOI
TL;DR: This work explicitly construct random hash functions for privacy amplification (extractors) that require smaller random seed lengths than the previous literature, and still allow efficient implementations with complexity $O(n\log n)$ for input length $n$ .
Abstract: We explicitly construct random hash functions for privacy amplification (extractors) that require smaller random seed lengths than the previous literature, and still allow efficient implementations with complexity $O(n\log n)$ for input length $n$ . The key idea is the concept of dual universal2 hash function introduced recently. We also use a new method for constructing extractors by concatenating $\delta $ -almost dual universal2 hash functions with other extractors. Besides minimizing seed lengths, we also introduce methods that allow one to use non-uniform random seeds for extractors. These methods can be applied to a wide class of extractors, including dual universal2 hash function, as well as to the conventional universal2 hash functions.

60 citations

Patent
19 May 1995
TL;DR: In this article, a system for spelling correction in which the context of a wordn a sentence is utilized to determine which of several alternative or possible words was intended is provided, where the probability that a particular alternative was the word that was intended was determined through Bayesian analysis utilizing multiple kinds of features of the context, such as the presence of certain characteristic words within some distance of the target word, or the presence that certain characteristic patterns of words and part-of-speech tags around a target word.
Abstract: A system is provided for spelling correction in which the context of a wordn a sentence is utilized to determine which of several alternative or possible words was intended. The probability that a particular alternative was the word that was intended is determined through Bayesian analysis utilizing multiple kinds of features of the context of the target word, such as the presence of certain characteristic words within some distance of the target word, or the presence of certain characteristic patterns of words and part-of-speech tags around the target word. The system successfully combines multiple types of features via Bayesian analysis through means for resolving egregious interdependencies among features. The system first recognizes the interdependencies, and then resolves them by deleting all but the strongest feature involved in each interdependency, thereby allowing it to make its decisions based on the strongest non-conflicting set of features. In addition, the robustness of the system's decisions is enhanced by the pruning or deletion from consideration of certain features, in one case by deleting features for which there is insufficient evidence in the training corpus to support reliable decision-making, and secondly by deleting features which are uninformative at discriminating among the alternative spellings of the target word under consideration.

59 citations

Patent
29 Oct 1998
TL;DR: A portable cellular phone includes audio input means, transmission means for transmitting to a calling/called party, audio information converted by the input means and character information input mean, and character memory as discussed by the authors.
Abstract: A portable cellular phone includes audio input means, transmission means for transmitting to a calling/called party audio information converted by the input means, character information input means, and character memory. The portable cellular phone further includes a digital camera which photographs an image and outputs image information, image memory which stores the image information, a system control section which links the image information of the digital camera or of the image memory to character information of the character memory, display means which displays linked information items, and changeover means which switches the image information received from the image memory to audio information in such a way that means for transmitting the audio information transmits the image information.

59 citations

Journal ArticleDOI
Hisao Taoka1, Isao Iyoda1, Hideo Noguchi1, Nobuyuki Sato, Taro Nakazawa 
TL;DR: The authors describe the basic characteristics of the digital simulator and present results obtained in real-time simulations.
Abstract: A digital simulator based on a hypercube-type massively parallel computer, the NCube2, has been developed. The simulator features: real-time simulation of a large power system which covers transient stability through long-term behavior with constant accuracy level in root mean square values; user-friendly man-machine interfaces which mimic the actual operating environment including interactive setting of several system parameters and real-time data presentation on a CRT; and high-speed A/D (analog to digital) converters, D/A (digital to analog) converters, and D/IO (digital input and digital output) interfaces are used to connect the digital simulator (power system dynamic model) to actual equipment. The authors describe the basic characteristics of the digital simulator and present results obtained in real-time simulations. >

59 citations

Patent
21 Jul 1995
TL;DR: In this paper, the addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of the flash memory devices, such that the address for the plurality of continuous logic blocks is respectively distributed into the plurality, and when block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two devices in which physical blocks to be erased exist.
Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

59 citations


Authors

Showing all 23025 results

NameH-indexPapersCitations
Ron Kikinis12668463398
William T. Freeman11343269007
Takashi Saito112104152937
Andreas F. Molisch9677747530
Markus Gross9158832881
Michael Wooldridge8754350675
Ramesh Raskar8667030675
Dan Roth8552328166
Joseph Katz8169127793
James S. Harris80115228467
Michael Mitzenmacher7942236300
Hanspeter Pfister7946623935
Dustin Anderson7860728052
Takashi Hashimoto7398324644
Masaaki Tanaka7186022443
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20224
2021327
20201,060
20191,605
20181,517
20171,090