Mitsubishi Electric

About: Mitsubishi Electric is a company organization based out in Ratingen, Germany. It is known for research contribution in the topics: Signal & Voltage. The organization has 23024 authors who have published 27591 publications receiving 255671 citations. The organization is also known as: Mitsubishi Electric Corporation & Mitsubishi Denki K.K..

Improvement of sidewall roughness in deep silicon etching

Abstract: The recently developed High Aspect Ratio Si Etch (HARSE) process is widely used for applications requiring silicon structures with high aspect ratios. This process relies on the alternation of sidewall passivation and silicon etching phases and enables the obtainment of high silicon etch rates and highly anisotropic profiles. This paper reports an innovative approach to improve the sidewall roughness through a multiple-step HARSE process using an ICP system. Unlike the standard HARSE process, the etching conditions for this new process are gradually altered in order to reinforce the silicon etch efficiency as a function of the silicon depth previously etched. Trenches with aspect ratios as high as 40 can be achieved. The sidewall roughness along the entire etching depth is less than 8 nm rms. In comparison with the standard HARSE process in which ripples appear on the trenches sidewall, the sidewall roughness is improved by a factor of 4.

Motion compensated digital video signal processing

Abstract: A method determines true motion vectors associated with a sequence of images. The images include fields made up of blocks of pixels. The method selects candidate feature blocks from the blocks of pixels. The candidate feature blocks have intensity variances above a threshold indicative of texture features. Candidate feature blocks in similarly numbered adjacent field intervals are compared to determine sets of displaced frame differences parameters for each candidate feature block. The true motion vectors for each candidate feature block are determined from a minimum weighted score derived from the difference parameters.

Electric Power Converter

Abstract: There are provided an electric power converter in which common-mode noise is suppressed without causing enlargement of components, increase in the number of components, a cost hike, and the like The electric power converter is provided with a capacitor ( 12 ) connected with the input terminal of the inverter circuit ( 13 a ), a noise suppression means ( 10 a, 10 b ) that is provided around at least one of input-side conductors connected with the input terminals of the inverter circuit ( 13 a ) and output-side conductors connected with the output terminals of the inverter circuit ( 13 a ), an electric quantity detector ( 11, 19 a, 19 b, 19 c ) that is provided in the input-side conductors or the output-side conductors at a position opposite to the inverter circuit with respect to the noise suppression means ( 10 a, 10 b ), and a control unit ( 20 ) that controls the inverter circuit ( 13 b ), based on an electric quantity detection signal from the electric quantity detector

Performance Analysis and Parallel Implementation of Dedicated Hash Functions

Abstract: This paper shows an extensive software performance analysis of dedicated hash functions, particularly concentrating on Pentium III, which is a current dominant processor. The targeted hash functions are MD5, RIPEMD-128-160, SHA-1 -256 -512 and Whirlpool, which fully cover currently used and future promising hashing algorithms. We try to optimize hashing speed not only by carefully arranging pipeline scheduling but also by processing two or even three message blocks in parallel using MMX registers for 32-bit oriented hash functions. Moreover we thoroughly utilize 64-bit MMX instructions for maximizing performance of 64-bit oriented hash functions, SHA-512 and Whirlpool. To our best knowledge, this paper gives the first detailed measured performance analysis of SHA-256, SHA-512 and Whirlpool.

An 8-bit high-speed CMOS A/D converter

Abstract: An 8-bit high-speed A/D converter has been developed in a 1.5-/spl mu/m bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimized. High speed (30 MS/s) and low power consumption (60 mW) have been obtained. Computerized evaluations such as the histogram test and the fast Fourier transform test have been used to measure dynamic performance. The linearity error in dynamic operation is less than /spl plusmn/1 LSB. Signal-to-peak-noise ratio is 40 dB at a sampling rate of 14.32 MS/s and an input frequency of 1.42 MHz.