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Institution

Mitsubishi Electric

CompanyRatingen, Germany
About: Mitsubishi Electric is a company organization based out in Ratingen, Germany. It is known for research contribution in the topics: Signal & Voltage. The organization has 23024 authors who have published 27591 publications receiving 255671 citations. The organization is also known as: Mitsubishi Electric Corporation & Mitsubishi Denki K.K..


Papers
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Patent
26 Jul 2010
TL;DR: In this paper, a DC/DC power converter where mean power consumption can be reduced over a wide range of DC voltage ratios is described, where a control circuit (120) changes a switching frequency (f) at which IGBTs (S1-S4) are turned ON/OFF in accordance with a voltage ratio (k) on the basis of the following equations, so that the magnitude (ΔI) of the current ripple flowing in a reactor (Lc) is a prescribed fixed value irrespective of the voltage ratio(k) (k = V2
Abstract: Disclosed is a DC/DC power converter wherein mean power consumption can be reduced over a wide range of DC voltage ratios. A control circuit (120) changes a switching frequency (f) at which IGBTs (S1-S4) are turned ON/OFF in accordance with a voltage ratio (k) on the basis of the following equations, so that the magnitude (ΔI) of the current ripple flowing in a reactor (Lc) is a prescribed fixed value irrespective of the voltage ratio (k) (k = V2 / V1) of the DC voltage conversion. When 1 ≦ k < 2: f = (V1 / (2 × L × ΔI)) × (k - 1) × (2 - k) / k When k > 2: f = (V1 / (2 × L × ΔI)) × (k - 2) / k

53 citations

Patent
30 Jan 2015
TL;DR: In this article, a macro block size determining unit 1 determines the size of each macro block on a frame-by-frame basis, and a macro blocks coding unit 3 determines a coding mode for each of the macro blocks divided by the macro block dividing unit 2, and codes pixel values in each macro blocks in the determined coding mode.
Abstract: A macro block size determining unit 1 determines the size of each macro block on a frame-by-frame basis. A macro block dividing unit 2 divides an inputted image into macro blocks each having the size determined by the macro block size determining unit 1. A macro block coding unit 3 determines a coding mode for each of the macro blocks divided by the macro block dividing unit 2, and codes pixel values in each of the macro blocks in the determined coding mode.

53 citations

Patent
Nobuya Uda1
09 May 2002
TL;DR: In this article, an analog input signal of a significant level generated in the external switching circuit is received at the analog input terminal of the one-chip microcomputer, and an A/D conversion start request signal is generated in an A-D converter start request generating circuit, and the digital data is readout to the CPU.
Abstract: An input circuit of a one-chip microcomputer is connected to an external switching circuit. When an analog input signal of a significant level generated in the external switching circuit is received at an analog input terminal of the input circuit, an A/D conversion start request signal is generated in an A/D conversion start request generating circuit and is sent to an A/D converter. The operation of the A/D converter is started in response to the A/D conversion start request signal, the analog input signal received at the analog input terminal is converted into digital data, and an A/D conversion finish signal is sent from the A/D converter to a CPU of the one-chip microcomputer. The operation of the CPU is started in response to the A/D conversion finish signal, and the digital data is readout to the CPU. Therefore, the A/D converter, the CPU or a clock is not operated to wait for an analog input signal generated in the external switching circuit, but the A/D converter is operated for the A/D conversion, and the CPU is operated to read out the digital data. Accordingly, an electric power consumed in the A/D converter, the CPU and the clock can be reduced.

53 citations

Proceedings ArticleDOI
01 Feb 1990
TL;DR: This work has developed a dynamic load balancing scheme which is applicable to OR-parallel programs in general and scalable to any number of processors because of this multi-level hierarchical structure.
Abstract: Good load balancing is the key to deriving maximal performance from multiprocessors. Several successful dynamic load balancing techniques on tightly-coupled multiprocessors have been developed. However, load balancing is more difficult on loosely-coupled multiprocessors because inter-processor communication overheads cost more. Dynamic load balancing techniques have been employed in a few programs on loosely-coupled multiprocessors, but they are tightly built into the particular programs and not much attention is paid to scalability. We have developed a dynamic load balancing scheme which is applicable to OR-parallel programs in general. Processors are grouped, and work loads of groups and processors are balanced hierarchically. Moreover, it is scalable to any number of processors because of this multi-level hierarchical structure. The scheme is tested for the all-solution exhaustive search Pentomino program on the mesh-connected loosely-coupled multiprocessor Multi-PSI, and speedups of 28.4 times with 32 processors and 50 times with 64 processors have been attained.

53 citations

Patent
10 Mar 2003
TL;DR: In this article, data read operations before and after the application of a data write magnetic field are executed using read modify write to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path.
Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

53 citations


Authors

Showing all 23025 results

NameH-indexPapersCitations
Ron Kikinis12668463398
William T. Freeman11343269007
Takashi Saito112104152937
Andreas F. Molisch9677747530
Markus Gross9158832881
Michael Wooldridge8754350675
Ramesh Raskar8667030675
Dan Roth8552328166
Joseph Katz8169127793
James S. Harris80115228467
Michael Mitzenmacher7942236300
Hanspeter Pfister7946623935
Dustin Anderson7860728052
Takashi Hashimoto7398324644
Masaaki Tanaka7186022443
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20224
2021327
20201,060
20191,605
20181,517
20171,090