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Institution

Mitsubishi Electric

CompanyRatingen, Germany
About: Mitsubishi Electric is a company organization based out in Ratingen, Germany. It is known for research contribution in the topics: Signal & Voltage. The organization has 23024 authors who have published 27591 publications receiving 255671 citations. The organization is also known as: Mitsubishi Electric Corporation & Mitsubishi Denki K.K..


Papers
More filters
Journal ArticleDOI
TL;DR: In this article, a fault location algorithm based on the Fourier analysis of a faulted network is presented, which embodies an accurate location by measuring only a local end data, and its fundamental theory is studied through digital computer simulations on a model power system.
Abstract: A fault location algorithm based on the Fourier analysis of a faulted network is presented. The algorithm embodies an accurate location by measuring only a local end data. Its fundamental theory is studied through digital computer simulations on a model power system. With the practical applications in mind, fast algorithms are then examined. Finally, the experimental results of a computerized fault locator applied to a laboratory system are presented.

129 citations

Journal ArticleDOI
10 Dec 2002
TL;DR: In this article, a high performance vector control system of an ac motor using a low-switching-frequency (2 kHz) pulsewidth-modulation voltage-source inverter with an output LC filter was proposed.
Abstract: This paper proposes a novel high-performance vector control system of an ac motor using a low-switching-frequency (2 kHz) pulsewidth-modulation voltage-source inverter with an output LC filter. Excellent high-speed response characteristics of the LC filter output voltage have been realized using a novel deadbeat control algorithm. As for the experimental results, the torque current response that is similar to the response of the conventional system without an LC filter has been obtained. In addition, it has been confirmed by simulation that errors of the LC filter constants within /spl plusmn/10% can be permitted.

129 citations

Journal ArticleDOI
TL;DR: A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed and the RB adder (RBA) circuit is improved so that it can make a fast addition of the RB partial products.
Abstract: A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

129 citations

Patent
16 May 1994
TL;DR: In this paper, an electronic document management system converts documents into electronic images which can be sequentially routed to individual users in a network system, which includes at least two work nodes for processing the documents where one of the nodes is a data entry work node.
Abstract: An electronic document management system converts documents into electronic images which can be sequentially routed to individual users in a network system. The network system includes at least two work nodes for processing the documents where one of the nodes is a data entry work node. The documents are subdivided into two or more subdivisions which are classified by subdivision type. The images are routed through the network system according to predefined routing schemes based on its subdivision type. The routing scheme for the documents includes at least one data entry node where data contained in the document is entered into a database. As the data is entered into the database, it is dynamically linked with its corresponding image which is also stored in the network.

129 citations

Patent
05 Feb 1996
TL;DR: Direct deposit messaging as discussed by the authors uses both sender-provided and receiver-provided information to process received messages and to deposit data directly in memory and to conditionally interrupt a host processor based on control information.
Abstract: A network protocol and interface using direct deposit messaging provides low overhead communication in a network of multi-user computers. This system uses both sender-provided and receiver-provided information to process received messages and to deposit data directly in memory and to conditionally interrupt a host processor based on control information. Message processing is separated into data delivery, which bypasses the host processor and operating system, and message actions which may or may not require host processor interaction. In this protocol, a message includes an indication of the operation desired by the sender, an operand specified by the sender and an operand which refers to some information stored at the receiver. The receiver ensures that the desired action is permitted and then, if the action is permitted, performs the action according to both the operand specified by the sender and the state of the receiver. The action may be message delivery, wherein the operands in the message specify values for use in various addressing modes including direct, indirect, post-increment and index modes. The action may also be conditionally generating an interrupt, wherein the operands are used, in combination with the receiver state, to determine whether a message requires immediate or delayed action. The action may also be an operation on a register in the network interface or on other information stored at the receiver.

128 citations


Authors

Showing all 23025 results

NameH-indexPapersCitations
Ron Kikinis12668463398
William T. Freeman11343269007
Takashi Saito112104152937
Andreas F. Molisch9677747530
Markus Gross9158832881
Michael Wooldridge8754350675
Ramesh Raskar8667030675
Dan Roth8552328166
Joseph Katz8169127793
James S. Harris80115228467
Michael Mitzenmacher7942236300
Hanspeter Pfister7946623935
Dustin Anderson7860728052
Takashi Hashimoto7398324644
Masaaki Tanaka7186022443
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20224
2021327
20201,060
20191,605
20181,517
20171,090