Showing papers by "Motorola published in 1974"

Silent call pager

Abstract: A pager that produces a vibratory alerting signal when a paging signal is received. Vibrating motion is created by a motor, internal to the pager, rotating a weight. The rotating weight initially presents a small torque load to the motor, but subsequently a large vibrating motion is created because the center of gravity of the rotating weight moves further away from the axis of rotation due to centrifugal force.

Intracranial pressure sensing device

Abstract: A fluid pressure sensor for use internal to the human body including a completely ceramic sectioned outer shell having an opening therein for allowing fluid access to a thin metal diaphragm member. The thin metal diaphragm member is disposed between the sectioned outer shell by diffusion bonding in order to limit exposure of the human tissue solely to the diaphragm member and the ceramic shell. A variable tuned LC circuit is responsive to fluid pressure for establishing a predetermined electrical parameter. The electrical parameter is capable of affecting an electromagnetically responsive electrical circuit means located external to the human body for providing data indicative of the fluid pressure. The thin diaphragm member constitutes one plate of the LC circuit and the remainder of the LC circuit is located beneath the thin diaphragm member so as to be protected from fluid and moisture.

Physics of Electromigration

Abstract: This survey paper on electromigration describes factors which govern the rate of electromigration and therefore relate to the lifetime of conductors stressed at high current density. These include the type of metal conductor, the conductor cross sectional area, lattice, grain boundary and surface diffusion effects, the addition of alloying elements, temperature and current density as well as the thermal conductivity of the substrate. The effect of gradients in temperature, current density, conductor composition and grain size on conductor lifetime are also discussed.

A quantitative study of emitter ballasting

Abstract: A theoretical and experimental study is carried out to quantitatively analyze the effect of emitter ballasting on thermal instabilities in high power density transistors. The analysis includes factors such as thermal resistance, emitter and base resistances, collector dissipation, etc., affecting thermal runaway. In particular, numerical computations are presented to describe current-voltage characteristics as they relate to thermal instability with emitter ballast resistance and the collector bias voltage as parameters. The agreement between theory and experiment is shown to be excellent. The study yields a minimum value of ballast resistance above which there is unconditional thermal stability.

Multiple interrupt microprocessor system

Abstract: A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. The digital system uses a multi-level interrupt circuit arrangement including a masked interrupt request input responsive to a multi-plexed interrupt request from peripheral circuits of the system and a non-masked interrupt request input which activates circuitry internal to the microprocessor chip for bypassing program control in initiating an interrupt sequence.

Interrupt circuitry for microprocessor chip

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Portable telephone system having a battery saver feature

Abstract: A battery saving system for a portable duplex communications system such as a portable telephone system includes a voice operated transmitter within each portable unit which automatically transmits radio signals upon application of audio signals thereto and discontinues transmission upon termination of the audio signals to conserve battery power. A companion receiver includes a fast acting squelch system to substantially eliminate the noise bursts occurring between transmissions by said portable unit.

Dielectrically isolated semiconductor devices

Abstract: The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

Muting circuit for a radio receiver

Abstract: A zero crossing detector and one shot circuit connected to receive audio frequency signals from a receiver and provide a pulse each time the signal crosses a reference level, first and second one shot timers connected to receive the pulses and provide pulses in response thereto which coincide with the zero crossing of a predetermined signal it is desired to mute, coincidence gates receiving the one shot pulses and the delayed pulses and cooperating with a missing pulse detector and a relay in the receiver to mute the receiver whenever the pulses from either of the one shot timers coincide with the pulses from the zero crossing detector, which coincidence indicates a signal of the frequency it is desired to mute.

Antenna pattern generator and switching apparatus

Abstract: A variable pattern antenna system including a plurality of radiating elements, a switching circuit for selectively applying signals to various ones of the radiating elements, a phase shifting circuit for shifting the phase of the signals applied to the elements, and a control circuit for operating the switching circuit and phase shifting circuit to cause variable phase signals to be applied to predetermined radiating elements for changing the pattern of the antenna, and a drive wave-shaping circuit to prevent abrupt switching and the spectrum spreading interference commonly known as ''''splatter'''' that would occur.

MOS DC Voltage booster circuit

Abstract: A MOSFET voltage booster circuit generates a stepped up DC voltage from a lower magnitude supply voltage and a periodic input signal. A plurality of such MOSFET voltage booster circuits, which are formed only from components integrated in the MOSFET integrated circuit chip, may be formed on the chip near corresponding sections of circuitry requiring a high DC bias signal. A free-running oscillator circuit may provide the required periodic input signal.

Method for filling grooves and moats used on semiconductor devices

Abstract: A process is disclosed for filling grooves, moats, and channels formed by both channel and anisotropic etching techniques. Basically the process is a two-step process to be performed on a wafer in which a channel and/or a moat has been formed. A P+ (boron) doped oxide is placed in the grooves or moats using spinon techniques followed by a uniform deposition of polycrystalline silicon over the entire wafer. Due to the spinning effects the P+ doped oxide is collected mostly in the grooves or moats. The P+ doped oxide that remains outside of the grooves and/or moats is removed using standard photolithographic procedures. The wafer is now heated to a temperature sufficient to drive the boron impurities from the P+ doped oxide into the polycrystalline silicon. A portion of a polycrystalline silicon now becomes heavily P+ doped. The remaining polycrystalline silicon remains undoped. The wafer is then etched by an etchant which effectively stops when the material being etched is highly P+ doped. In this manner a portion of the remaining undoped polycrystalline material is removed and the highly doped polycrystalline material is left in the channels and/or moats. The above can be repeated until the moats or channels are completely filled.

Supporting and connecting structure for electric device

Abstract: A structure for supporting a portable electric device and for making electrical connections thereto for energizing the device and connecting the same to external apparatus. The structure shown is particularly adapted to support a portable radio for use in a vehicle, and for automatically connecting the radio to an electric current supply and/or an antenna, and/or to other external apparatus. The structure can also be used to lock the radio into the frame, protecting it against unauthorized removal. The supporting structure includes a housing for receiving the electric device, which is slidably mounted in a frame, with movement of the housing causing movement of connectors thereon into operative engagement with electrical connectors on the device. The frame may include a cam engaged by the actuator of a connector, to move the connector as the housing slides within the frame. The structure for supporting a portable radio may include first and second connectors moving in sequence as the housing with the radio therein slides within the frame, with the first connector making electrical connections to the radio and also accurately positioning the radio within the housing, and the second connector then moving to make connection with the radio.

CMOS voltage controlled oscillator

Abstract: A CMOS voltage controlled oscillator is described. This CMOS voltage controlled oscillator is a linear CMOS circuit and exhibits an infinite current gain, a near infinite input impedance, a very high voltage gain with a corresponding low power consumption. Additionally, the oscillator is capable of operating over a wide range of DC supply voltages. Because the circuit is of CMOS design its complexity is much less than corresponding circuits made using bipolar devices or field effect transistors. This CMOS voltage controlled oscillator comprises a complementary current source generator for providing a current source as a charging current and a current sink as a discharging current of equal magnitude for the timing capacitor of the circuit. This charging and discharging current are each linearly proportional to the input controlling voltage. A high speed voltage comparator is responsive to the voltage of the timing capacitor and the voltage from an hysteresis feedback circuit for providing fast acting driving voltage for the output stage. A linear amplifier output stage is responsive to the high speed voltage comparator for providing ultra-fast changing signals for wave shaping purposes. An hysteresis feedback loop responsive to the output stage and connected as one input to the voltage comparator provides two threshold states for the voltage comparator.

Hermetically sealed keyboard type assembly with elastomeric electrical connecting link between switch and component modules

Abstract: A housing having key portions of a resilient pad extending therethrough with a metal impregnated elastomer pad overlying the rear surface thereof, a sheet of insulating material having openings therethrough corresponding with the key portions and a plurality of contact areas on a printed circuit board overlying the insulating sheet and having a plurality of contacts on the rear surface thereof, a connecting link formed of a second sheet of insulating material having a plurality of areas of metal impregnated elastomeric material extending therethrough and corresponding in position with the contacts, a second PC board having a plurality of contacts in contact with the elastomeric areas of the connecting link and a frame compressing all of the components together to provide an electrical contact to the elastomeric material in the connecting link and complete a circuit between various contacts on the two printed circuit boards and provide a weather-tight multi-push button switch.

Negative resistance high-q-microwave oscillator

Abstract: A high-Q negative resistance microwave oscillator is disclosed which comprises a semiconductor diode, suitably a Gunn or Impatt diode, located within a low-Q resonant structure or cavity for generating a carrier frequency, f; and another waveguide cavity tuned to f having a very high-Q relative to the first cavity, and which is optimally coupled to the low-Q cavity. The microwave energy generated in the low-Q cavity is coupled to the high-Q cavity which reflects energy at frequency, f, back to the low-Q cavity to maintain oscillations at the aforementioned frequency. The microwave energy thus developed is supplied directly to a load by a microwave passage that is coupled to the low-Q cavity. An internal microwave load is employed to dissipate undesired frequencies thereby restricting these frequencies from being generated within the low-Q cavity and therefore enhancing the oscillator''s frequency stability.

MOS current limiting output circuit

Abstract: An MOS push-pull driver circuit includes a pull up MOSFET and a pull-down MOSFET coupled to an output node A polycrystalline silicon current limiting resistor is connected between the drain of the pull-up MOSFET and the supply voltage conductor to provide a closer tolerance output current than is normally feasible for state-of-the-art MOSFET manufacturing processes

Chip topography for MOS interface circuit

Abstract: The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite edge of the chip and a register section centrally located on the chip. Separate power supply buses are used to supply a ground voltage to the buffer and register sections. Data bus buffers are arranged to allow the pins of the enclosing semiconductor package to correspond to data bus pins of a separate microprocessor chip. Register sections are offset on the surface of the peripheral interface adaptor chip in such a way as to facilitate nesting of the conductors coupled to the buffer circuit section. Identical buffer cells and custom drawn cells are both utilized so as to optimize use of semiconductor chip area.

Indicating system using multicolor light emitting diodes

Abstract: An indicating system for a radio receiver is formed of an indicator and associated control circuitry. The indicator is comprised of two emitting diodes wired in parallel and in reverse polarity, and encapsulated in a translucent package. Each diode in an indicator emits light of a visibly distinct wavelength when energized. The control circuitry causes a change in polarity of bias voltage applied to the indicator, and, in so doing a change in color of the indicator. With appropriate control circuitry, the color of the indicator indicates whether the receiver is tuned to an AM or FM station, or whether the station is broadcasting in mono or stereo. The indicator can be mounted to the dial pointer causing a change in pointer color with a change in receiver function. Additionally, the amount of current through the light emitting diodes and thus the intensity of emitted light may be varied in accordance with a parameter variation as, for example, accuracy of receiver tuning.

Method of making universal wafer carrier

Abstract: A semiconductor wafer carrier is described for use in a high wear environment. The constituent metal parts are preferably made of aluminum. The elements for holding a plurality of wafers are manufactured by extruding grooves in a pair of side members. An alignment notch is formed simultaneously with the wafer holding grooves. This carrier is of integral construction wherein the preferred embodiment has its members joined by staking. The lowcost feature of the carrier is of prime importance because of the high volume of such devices used. The wafer carrier is universal in nature insofar as it is compatible for use in a plurality of automatic wafer handling machines. This feature is important because it reduces, if not completely eliminates the operator training which is otherwise required for identifying the correct wafer carrier to be used with a corresponding piece of automatic wafer handling machinery.

CMOS synchronous binary counter

Abstract: A multi-state CMOS synchronous binary counter is implemented utilizing a CMOS transmission gate look-ahead carry circuit requiring only a fraction of the area required for AND or NAND gate carry structures.

Fixture and system for handling plate like objects

Abstract: A system for handling plate like objects (e.g., semiconductor wafers) includes a gas actuated fixture having a surface for releasably picking up the plate like objects (e.g., by Bernoulli effect). Means is provided for moving the pickup fixture in a plane of motion from a first to second position. Means forming a part of the pickup fixture (e.g., a selectively pressured bellows) moves the pickup surface orthogonally to the plane of motion. An air track or other conveyer for the plate like objects includes means for restraining the objects beneath the first position. Means for positioning successive locations of a carrier for the plate like objects positions the successive locations beneath the second position. In operation, the system picks up the plate like objects from the conveyer, loads them onto the carrier, then unloads them from the carrier and returns them to the conveyer, all without subjecting the objects to human contamination.

Mos data bus control circuitry

Abstract: An MOS micro-processor circuit includes an output circuit which provides data internally generated during a particular clock pulse during a write cycle. A control signal enables the output circuit to maintain data at a valid logic level at the output after the end of said clock pulse. The output is controlled to provide a very high output impedance at the output except during said clock time or during said control signal. The circuit includes two two-input NOR gates cascaded and having a common enable input generated by an enable circuit. The enable circuit has as inputs the control signal and the output of read/write circuitry and generates a signal which enables the NOR gates during a write cycle or during the control signal. The input of the first NOR gate is coupled to a circuit generating an internal data signal.

Tunable antenna coupling circuit

Abstract: Tunable antenna coupling circuit for applying signals of different frequencies between an antenna and a transmitterreceiver, including a series circuit having a plurality of inductance sections and one or more shunt circuits providing capacitance between the series circuit and a reference potential. Reed switches are connected across the inductance sections, and selectively connect the capacitors in the shunt circuits, to thereby control the effective values in the circuit to match the impedance of the antenna at different frequencies to efficiently apply signals between the antenna and the transmitter-receiver. The reed switches are controlled by a channel selector having positions for the different channels (frequencies) to be used, which is coupled to the reed switches through a diode matrix for selectively operating the switches. The position of the channel selector controls the operation of predetermined ones of the reed switches to provide the desired coupling impedances for each channel. The values of inductance of the sections and the values of the capacitors have a binary relation so that by the selective connection thereof in the coupling circuit, a wide range of inductance values and capacitance values are obtained in small incremental steps.

Alphanumeric terminal for a communications system

Abstract: An alphanumeric terminal providing a digital message having a fixed portion consisting of the address of the receiver in sixteen bits, followed by a repeat of the address in sixteen bits, a status indication in four bits, a request in four bits and an acknowledge plus an indication of whether text follows in two bits; and a variable portion consisting of a text message of zero to 384 bits, which fixed and variable portions of the message have parity bits inserted after each digital word and are delayed and interleaved (every other bit) with a similar undelayed message to form a composite message, which composite message is preceded by a pseudo random code of 127 bits The terminal also includes noise and error detection circuitry, associated with the receiver, which separates the two interleaved messages and compares them for similarity, checks the parity bits for correctness and compares the amplitude of each bit to a predetermined upper and lower level to determine whether the bit is noise or a portion of the signal From the various noise and error checks the terminal then provides a decision as to whether a digital word is good or bad and, if the digital word is in error and comes within the text portion of the message, an asterisk appears in the visual display so that the operator can mentally determine what the character should be

Multiple parameter monitoring and readout system with sampling of parameters of higher priority than the highest parameter which is out of tolerance

Abstract: Apparatus for monitoring and indicating parameter conditions within a system. Signals are generated by sensors which monitor parameter state. The signals are sensed via a multiplexing scheme, each signal being compared to an individually programmed reference. Should a parameter signal exceed the reference, a corresponding indicator is activated. Each parameter is prioritized such that a parameter signal which exceeds its reference will cause the multiplex network to sequentially sense only that parameter and all other parameters of a higher priority. Further refinements allow the readout of the value of a parameter signal if the parameter exceeds its reference or if such readout is manually selected.

Interface adaptor having control register

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to a control register, the data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

Electronic tuning system for television receivers

Abstract: An electronic tuning control system for television receivers employs several different functional integrated circuit modules to effect channel selection either locally at the receiver itself or by remote control. The system includes a control circuit which permits sequential scanning or stepping of the different channels in either the ''''up'''' or ''''down'''' direction. A provision is made for setting tuning control potentiometers for each channel to either a first range of settings indicative of ''''preferred'''' channels to which the receiver can be tuned or to a second range indicating that no tuning or channel selection is to be effected for ''''non-preferred'''' channels. The second range then is utilized to cause the receiver to automatically skip over such nonpreferred channels and scan only those channels having a preferred setting. In addition, direct selection of a channel is effected by closing individual switches associated with each channel. The direct selection circuitry operates through the scanning circuitry in conjunction with the skip mode circuitry to effect substantially instantaneous direct channel selection.

Phase locked loop lock detector and method

Abstract: Apparatus and method for determining when a phase lock loop is in a state of lock is disclosed. The input frequency and the VCO frequency of a phase locked loop are combined by a difference multiplier to produce a signal having their difference frequency. The difference frequency signal is transformed into a squarewave by a limiter and the squarewave is then fed into a binary counter which counts the frequency of the squarewave pulses. Circuitry including a clock, two monostables, an AND gate, and a one cycle memory flip-flop periodically monitors the count of the binary counter and produces a signal indicating a state of unlock when the count of the binary counter exceeds a predetermined limit. An inhibit signal which prevents the binary counter from continuing to count is generated when the predetermined count limit has been reached in any one monitored time period.

External data control preset system for inverting cell random access memory

Abstract: A preset conductor adapted to receive a preset signal externally or internally applied thereto presets the data control register of a dynamic MOS random access memory having an array of inverting storage cells therein. A MOSFET is connected between a storage node of each of the data control cells and the data control register and a ground conductor. The preset conductor is connected to the gate electrode of each of the preset MOSFETs.