Motorola

About: Motorola is a company organization based out in Schaumburg, Illinois, United States. It is known for research contribution in the topics: Signal & Communications system. The organization has 27298 authors who have published 38274 publications receiving 968710 citations. The organization is also known as: Motorola, Inc. & Galvin Manufacturing Corporation.

Vehicle locating system utilizing global positioning

Abstract: A vehicle locating system (200) includes a beacon (108) carried by a vehicle, a tracking control station (106) for generating a beacon activation signal (110) which enables the beacon (108) to broadcast a vehicle identification signal (112), and one or more mobile communication devices (116, 118) which include a first receiver (516) utilized to receive a location signal (122) identifying a geographic location of a mobile communication device, and a transceiver (406) utilized to provide communication between said mobile communication device and a communication system controller. The one or more mobile communication devices (116, 118) further include a second receiver (502) utilized to receive the vehicle identification signal (112) broadcast by the beacon (108), and a vehicle tracking controller (520), responsive to the vehicle identification signal (112) which is received, for controlling a transmission of the vehicle identification signal (112) and the location signal (122).

Event-driven cell scheduler and method for supporting multiple service categories in a communication network

Abstract: The event scheduler (100; 200) and method (300) of the present invention solve the problem of mixing multiple service categories on the same physical link or media by utilizing a calendar queue scheduling method (i.e., based on prior actual transmission times of previous packets). The event-driven cell scheduler is, for example, used in an asynchronous transfer mode ATM network and may, for example, be embodied in software, hardware and firmware.

Isophoric arrays-massively thinned phased arrays with well-controlled sidelobes

Abstract: Traditional filled phased arrays have an element placed in every location of a uniform lattice with half-wavelength spacing between the lattice points. Massively thinned arrays have fewer than half the elements of their filled counterparts. Such drastic thinning is normally accompanied by loss of sidelobe control. This paper describes a class of massively thinned linear and planar arrays that show well-behaved sidelobes in spite of the thinning. The term isophoric is derived from Greek roots to denote uniform weight. In isophoric arrays, element placement based on difference sets forces uniformly weighted spatial coverage. This constraint forces the array power pattern to pass through V uniformly spaced, equal, and constant values that are less than 1/K times the main beam peak, where V is the aperture size in half-wavelengths and K is the number of elements in the array. The net result is reduced peak sidelobes, especially when compared to cut-and-try random-placement approaches. An isophoric array will exhibit this sidelobe control even when the array has been thinned to the extent that K is approximately the square root of V. Where more than one beam must be generated at a time, isophoric array designs may be used to advantage even within a traditional filled array. By "interweaving" two isophoric subarrays within a filled array and by appropriate cyclic shifting of the element assignments over time, two independent antenna power patterns can be generated, each with a sidelobe region that is approximately a constant value of 1/(2K) relative to the main beam, where K is the number of elements in the subarray.

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Abstract: Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC, alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more cost-effective application of RET.

Antenna(s) and electrochromic surface(s) apparatus and method

Abstract: One or more electrochromic surfaces ( 11 ) (formed on rigid or flexible carrier surfaces) are used in various ways with one or more radio frequency energy radiating elements ( 10 ) and/or guiding elements ( 91 and 120 ) to lend selective reflectivity to achieve greater resultant control over directionality, gain, phase, and/or shape of the radiated energy.