Institution
Motorola
Company•Schaumburg, Illinois, United States•
About: Motorola is a company organization based out in Schaumburg, Illinois, United States. It is known for research contribution in the topics: Signal & Communications system. The organization has 27298 authors who have published 38274 publications receiving 968710 citations. The organization is also known as: Motorola, Inc. & Galvin Manufacturing Corporation.
Papers published on a yearly basis
Papers
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12 Sep 1994TL;DR: In this article, a fax system is automated by using a modem, a computer, and an office network which coupled the computer (12) to a plurality of end-user computers (26).
Abstract: A fax system is automated herein by using a modem (10), a computer (12), and an office network which coupled the computer (12) to a plurality of end-user computers (26). A fax is received by the computer (12) through the modem (10). Once the fax is received by the computer (12), a program (14) stores the fax in a computer file (15) in a non-text format. Code (18) converts the non-text format of file (15) to a text format (17) which is read by a pattern recognition program (18). The program (18) determines, from the file (17), a destination of the fax document. The destination can be one or more of a printer (24), a computer in the plurality of computers (26), a default computer, or a default storage location (e.g., disk storage). A log file (19) is kept by computer (12) to record the operations of the computer (12) and receipt and routing information regarding received faxes. The control code (22) coordinates the other programs in memory (13).
147 citations
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16 Dec 1991TL;DR: In this article, a semiconductor wafer level package is used to encapsulate a device fabricated on a silicon substrate wafer before dicing of the wafer into individual chips, where a cap wafer is bonded to the semiconductor substrate using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity.
Abstract: A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.
147 citations
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12 Sep 1990TL;DR: In this article, an improved minimal comprehension time format was proposed to provide vehicle navigation information to the operator in an improved minimization time format, and allowed the vehicle operator to select for himself how to recover from an off route condition.
Abstract: Land vehicle navigation apparatus (10) with a visual display (16, 20) is provided. The apparatus provides a visual display of a calculated navigation route (22) with a visual indication (23) of the direction of desired travel along the navigation route. An off route map display portion (28) is provided which has the visual navigation route display (22) in one color and, in a second contrasting color, a visual display (24, 26) of actual vehicle travel. A separate additional feature is that an off route display (20) provides a visual display portion (29) of a plurality of operator selectable off route recovery options (1-6). Off route recovery means (12, 49-63) are provided such that the vehicle operator can implement the visually displayed recovery options. The result is a navigation system which visually provides vehicle navigation information to the vehicle operator in an improved minimal comprehension time format, and allows the vehicle operator to select for himself how to recover from an off route condition.
147 citations
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18 Sep 2002TL;DR: In this paper, a method for determining values for parity check bits (p 1,.., p m ) based on a current symbol set (s 1,..., s k ).
Abstract: The present invention encompasses a method for determining values for parity check bits (p 1 , . . . , p m ) based on a current symbol set (s 1 , . . . , s k ). The method comprises the steps of receiving the current symbol set (s 1 , . . . , s k ) and using a transformation of a matrix to determine the parity check bits. The first N 2 columns of the matrix is defined that for column i, 1≦i≦└m/2┘, a value of 1 is assigned to row position i and a value of 1 is assigned to row position i+└m/2┘, all other row positions have a value of 0. Additionally for column i, └m/2┘+1≦i≦N 2
147 citations
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01 Jun 1990TL;DR: In this paper, a method for translating complex process flow networks into plans or schedules for the manufacturing of products or the performance of other organizational activities is disclosed, which maintains a time-valued list of existing commitments to resources.
Abstract: A method for translating complex process flow networks into plans or schedules for the manufacturing of products or the performance of other organizational activities is disclosed. The method maintains a time-valued list of existing commitments to resources. Allocations of these resources are made to lots during a simulation procedure which calculates a resulting plan's timing data. The method simulates higher priority lots before it simulates lower priority lots. A simulation evaluates the process flow description to obtain the relative order of consuming and releasing resources, resource attributes and related capabilities, initial minimum timing requests, and process control rules. The simulation uses the list to determine when resources may be used without impacting prior commitments of the resources. In addition, the simulation forces the allocations to conform to the process control rules. The resulting timing data is merged into the processing plan, and resource commitments are then made to the simulated resource. When lower priority lots are simulated, commitments have already been made to higher priority lots. Thus, the lower priority lots cannot receive resource allocations which impact the higher priority lots. However, the lower priority lots may receive allocations which occur prior to contending allocations to higher priority lots.
147 citations
Authors
Showing all 27298 results
Name | H-index | Papers | Citations |
---|---|---|---|
Georgios B. Giannakis | 137 | 1321 | 73517 |
Yonggang Huang | 136 | 797 | 69290 |
Chenming Hu | 119 | 1296 | 57264 |
Theodore S. Rappaport | 112 | 490 | 68853 |
Chang Ming Li | 97 | 896 | 42888 |
John Kim | 90 | 406 | 41986 |
James W. Hicks | 89 | 406 | 51636 |
David Blaauw | 87 | 750 | 29855 |
Mark Harman | 83 | 506 | 29118 |
Philippe Renaud | 77 | 773 | 26868 |
Aggelos K. Katsaggelos | 76 | 946 | 26196 |
Min Zhao | 71 | 547 | 24549 |
Weidong Shi | 70 | 528 | 16368 |
David Pearce | 70 | 342 | 25680 |
Douglas L. Jones | 70 | 512 | 21596 |