National Institute of Technology, Meghalaya

About: National Institute of Technology, Meghalaya is a education organization based out in Shillong, India. It is known for research contribution in the topics: Control theory & Electric power system. The organization has 503 authors who have published 1062 publications receiving 6818 citations. The organization is also known as: NIT Meghalaya & NITM.

Optimization of reversible circuits using triple-gate templates at quantum gate level

Abstract: The paper presents an approach for optimizing a reversible netlist consisting of multiple-control Toffoli (MCT) gates with the objective of reducing quantum cost. The MCT gates are first decomposed into smaller gates with up to three control lines, and then a template matching method is applied on the netlist for optimization. The templates are constructed by considering all possible 3-gate sequences with up to four lines. This work constitutes an extension of a previous work by Dueck et al., where 2-gate sequences were considered in the templates. The input gate netlists are generated from the reversible benchmarks available in RevLib, followed by Barenco decomposition to produce Toffoli gates with at most three control connections. The proposed approach is applied on these netlists, and the final quantum cost calculated. Experimental results on standard benchmarks show that the method can lead to reductions in quantum cost.

Analysis of Flux Density in PMSM with Constant Mutual Flux Linkage Control Strategy Using FEM Model

Abstract: This paper presents flux density analysis of the Permanent Magnet Synchronous Machine in a closed-loop system. This system is developed in co-simulation with Ansys software using the FEM model of the machine. Here the vector control technique with constant mutual flux linkage control strategy is implemented. Different parameters such as electromagnetic torque, speed, stator current, flux density at different parts of the stator is analyzed in different operating conditions. However, the losses of motor highly depend on the rate of change of flux density, which is the utmost factor while designing Motor drive. The novelty of the paper implies the consideration of flux density variation in different parts of the stator core under the different test cases. However, in case of MATLAB/Simulink it's not possible to consider these losses inherently. The FEM model of the PMSM is insinuated to the practical model of the motor. Hence this analysis will be helpful for the designer to improve the drive system towards practical applications.

Characterizing Single Line to Ground (SLG) Events with Indian Power Grid’s Synchrophasor Data

Abstract: The availability of Phasor Measurement Units (PMUs) and power system there of opens new avenues for automated monitoring and control of power system. A first step to automated, real time power system control is to detect and classify power system events in an online fashion. The Indian power grid (IPG) has also introduced synchrophasor technology and has been fast progressing to install over 1700 PMUs across the country. The challenge however remains to use such PMU data for online event detection and classification for an automated control. Such as event classifier would require data driven characteristics of different events to be extracted. In this paper, an attempt has been made to characterize a very common transmission line event, namely, single line to ground (SLG) events (faults) based on data collected from PMUs from the Northern region of the IPG.

Integer division technique for signal processing applications

Abstract: Algorithmic implementation of integer division technique based on ancient Vedic mathematics is reported in this paper. The potentiality of the 'Nikhilam Navatascaramam Dasatah (NND)' (all from 9 and last from 10)' sutra of Vedic mathematics was adopted to implement the high speed integer division. Optimized 4221 BCD encoding technique was incorporated with Vedic mathematics, to implement such divider for practical signal processing applications. Propagation delay and dynamic switching power consumption of division circuitry were minimized significantly through stage reduction techniques of such sutra (formulae). The functionality of the division circuitry was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx tool (VHDL language). The propagation delay of the resulting 6÷3 digit divisor circuitry was only ~41ns and consumed ~93mW power. Amalgam-nation of BCD arithmetic with ancient Vedic mathematics, substantial amount of iterations were eliminated owing to ~20% reduction in delay and ~12% reduction in power from its counterpart.