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Institution

National Institute of Technology, Meghalaya

EducationShillong, India
About: National Institute of Technology, Meghalaya is a education organization based out in Shillong, India. It is known for research contribution in the topics: Control theory & Electric power system. The organization has 503 authors who have published 1062 publications receiving 6818 citations. The organization is also known as: NIT Meghalaya & NITM.

Papers published on a yearly basis

Papers
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Proceedings ArticleDOI
01 Apr 2018
TL;DR: Zeta converter is used as power processing stage in this paper to optimize power processing of solar photovoltaic system and HESS to overcome the limitations associated with conventional DC-DC converters.
Abstract: The increasing importance of renewable sources in the field of automotive sector encourages the use of solar photovoltaic (PV) system powered brushless DC motor (BLDC) drives. To overcome the limitations associated with conventional DC-DC converters, zeta converter is used as power processing stage in this paper to optimize power processing. The extraction of maximum power from solar PV system is done by providing switching pulses to zeta converter through incremental conductance (INC) maximum power point tracking (MPPT) algorithm. Integration of hybrid energy storage system (HESS) is employed to maintain constant voltage across the BLDC motor drive despite of variation in power output of solar PV system. A dual loop control strategy is employed for power management between solar PV system and HESS. The performance of the proposed system for variation in irradiation levels and load torque is demonstrated using MATLAB/Simulink. The real-time validation of the proposed controller is done through the Xilinx system generator platform interfaced with Zynq ZC-702 FPGA kit.

1 citations

Book ChapterDOI
01 Jan 2020
TL;DR: In this article, the fabrication and characterization of a primary side controlled flyback converter is carried out and the converter design specifications for Discontinuous Mode Conduction (DCM) of the converter are derived and used for simulation and designing purpose.
Abstract: In this paper, the fabrication and characterization of a current mode, primary side controlled Flyback converter is carried out. Furthermore, the converter design specifications for Discontinuous Mode Conduction (DCM) of the converter are derived and used for simulation and designing purpose. The simulated results are then verified with the characterization results using a 30 W street light.

1 citations

Book ChapterDOI
01 Jan 2020
TL;DR: Among the 7:3 compressors, the design utilizing the TG-based XOR gate is exhibiting least power consumption and the least delay is exhibited by the design which is based upon mirror circuit-basedXOR gate.
Abstract: This paper presents the power and delay comparison of 7:3 compressor circuit designed using three different architectures of XOR gate which are based upon mirror circuit, 4-transistor, (4-T) and transmission gate (TG). The compressors have been implemented in transistor level at 180 nm technology and the functionality is verified in Cadence-spectre. Among the 7:3 compressors, the design utilizing the TG-based XOR gate is exhibiting least power consumption and the least delay is exhibited by the design which is based upon mirror circuit-based XOR gate.

1 citations

Proceedings ArticleDOI
01 Dec 2019
TL;DR: A compact CAM cell employing a high-speed comparison and evaluation is presented for a segmented NOR match-line (ML) with reduced ML capacitance, capable of operating efficiently at relatively low supply voltage and worst process corner.
Abstract: Content addressable memory (CAM) is used as a hardware in lookup intensive applications Despite high-speed feature, power consumption is the major limitation in CAM design In this work, a compact CAM cell employing a high-speed comparison and evaluation is presented for a segmented NOR match-line (ML) with reduced ML capacitance The non-pipeline CAM architecture minimizes switching activity of precharge and search at the cost of negligible overhead of a ML precharge and decision block A 64×32-bit proposed macro is realized using 45-nm CMOS technology Post-layout simulations at 11 V shows that proposed architecture achieves 20360 ps search time while dissipating only 107 fJ/bit/search Consequently, it leads to 7124% and 8485% energy-delay-product reductions over a conventional CAM and local-NOR global-NAND CAM, respectively The proposed CAM based on two-segment configuration delivers ML power reductions of 1226%-6227% over the two CAMs The proposed design is capable of operating efficiently at relatively low supply voltage and worst process corner

1 citations


Authors

Showing all 517 results

NameH-indexPapersCitations
Sudip Misra485359846
Robert Wille434576881
Paul C. van Oorschot4115021478
Sourav Das301744026
Mukul Pradhan23531990
Bibhuti Bhusan Biswal201551413
Naba K. Nath20391813
Atanu Singha Roy19481071
Akhilendra Pratap Singh19991775
Abhishek Singh191071354
Vinay Kumar191301442
Dipankar Das19671904
Gayadhar Panda181231093
Gitish K. Dutta16261168
Kamalika Datta1569676
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20237
202236
2021191
2020220
2019184
2018155