National Institute of Technology, Meghalaya

About: National Institute of Technology, Meghalaya is a education organization based out in Shillong, India. It is known for research contribution in the topics: Control theory & Electric power system. The organization has 503 authors who have published 1062 publications receiving 6818 citations. The organization is also known as: NIT Meghalaya & NITM.

A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar

Abstract: Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.

Fano Scattering: Manifestation of Acoustic Phonons at the Nanoscale.

Abstract: Size-dependent asymmetric low-frequency Raman line shapes have been observed from silicon (Si) nanostructures (NSs) due to a quantum confinement effect. The acoustic phonons in Si NSs interact with an intraband quasi-continuum to give rise to Fano interaction in the low-frequency range. The experimental asymmetric Raman line shape has been explained by developing a theoretical model that incorporates the quantum-confined phonons interacting with an intraband quasi-continuum available in Si NSs as a result of discretization of energy levels with unequal separation. We discover that a phenomenon similar to Brillouin scattering is possible at the nanoscale in the low-frequency regime and thus may be called “Fano scattering” in general. A method has been proposed to extract information about nonradiative transitions from the Fano scattering data where these nonradiative transitions are involved as an intraband quasi-continuum in modulation with discrete acoustic phonons.

BDD based synthesis of Boolean functions using memristors

Abstract: Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.

A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using $N$ -Gate Lookahead

Abstract: With recent interest in reversible and quantum computation, research in synthesis of reversible and quantum circuits has increased in momentum. With additional requirements of neighborhood interactions among qubits (with two basis states) being a necessity in some physical realizations, several works on obtaining nearest neighbor quantum gate realization by inserting SWAP gates have been reported. These methods are based on two broad optimization approaches, one based on global ordering, where qubits are ordered over the whole netlist, and the other based on local ordering for minimizing SWAP gate insertions on smaller segments of netlists. Further reductions in cost are possible by using multi-valued qudits that have more than two basis states. The present paper considers a quantum circuit based on the NCV library, and proposes a better SWAP gate insertion method based on local ordering that uses an $N$ -gate lookahead approach to reduce cost. Experimental results on benchmark circuits and comparison against published works confirm the benefits of the proposed approach, with improvements over reported works obtained in the range of 27%–43% on the average and 54%–63% in the best case. The method is also scalable for larger circuits, with the longest runtime observed as 10 minutes.