scispace - formally typeset
Search or ask a question
Institution

National Institute of Technology, Meghalaya

EducationShillong, India
About: National Institute of Technology, Meghalaya is a education organization based out in Shillong, India. It is known for research contribution in the topics: Control theory & Electric power system. The organization has 503 authors who have published 1062 publications receiving 6818 citations. The organization is also known as: NIT Meghalaya & NITM.

Papers published on a yearly basis

Papers
More filters
Journal ArticleDOI
TL;DR: This work focuses on a new approach for BSS in speech processing applications by considering the second-order statistics of the speech signals based on a canonical correlation approach and results highlight the better performance of the proposed method as compared to the state of the art approaches.
Abstract: Separation of blind source signals from a mixture remains an open issue. Many algorithms have been proposed for blind source separation (BSS) in the literature, but none outperforms the other. Most of the earlier BSS methods were based on the assumption that the sources are independent and non-Gaussian. From the literature, it is observed that speech signals are modelled using Gaussian models. This work focuses on a new approach for BSS in speech processing applications by considering the second-order statistics of the speech signals based on a canonical correlation approach. The performance of the algorithm is analyzed using signal-to-interference ratio, signal-to-distortion ratio, signal-to-artifact ratio and signal-to-noise ratio. Simulation results highlight the better performance of the proposed method as compared to the state of the art approaches like principal component analysis, singular value decomposition and independent component analysis algorithms.

13 citations

Journal ArticleDOI
TL;DR: The results are compared with state-of-the-art literature and conclude that the proposed work with 36x36 block size architecture is suitable for ultra-high definition (UHD) resolution based consumer applications due to its occupancy of moderate amount of resources and higher processing speed.
Abstract: This paper presents a hardware architecture using mixed pipelined and parallel processing for Deblocking Filter (DBF)in High Efficiency Video Coding (HEVC) standard. The objective of the proposed work is to achieve low latency architecture for the DBF stage in HEVC. The work investigates the processing of different sizes of coding unit (CU) by partitioning each frame into blocks of different sizes (8x8, 16x16, 32x32 and 64x64). In order to execute filtering on multiple edges simultaneously without affecting the neighboring blocks, the block sizes have been increased to 12x12, 20x20, 36x36 and 68x68 with respect to aforementioned sizes. Moreover, the horizontal and vertical filtering of the frame is performed in a streaming fashion. The proposed work is implemented on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms. The results are compared with state-of-the-art literature and conclude that the proposed work with 36x36 block size architecture is suitable for ultra-high definition (UHD) resolution based consumer applications due to its occupancy of moderate amount of resources and higher processing speed.

13 citations

Journal ArticleDOI
TL;DR: In this paper, a micro-electrical discharge machining (μEDM) is used to produce precise and high-quality features in carbon fiber-reinforced polymers (CFRP) for efficient spark generation.
Abstract: Machining of carbon fiber-reinforced polymers (CFRP) by traditional processes is quite challenging as damages namely breakage of fibers, delamination, and fiber pull-out occur during machining. Therefore, non-traditional machining process namely micro-electrical discharge machining (μEDM) is emerging to produce precise and high-quality features in CFRP. In this work, for machining CFRP, μEDM method coupled with rotary tool and assisting-electrode was used for efficient spark generation. Grey relational analysis (GRA) was performed to optimize the machining parameters viz. voltage (100, 130, 160, and 190 V), pulse duration (10, 20, 30, and 40 μs), and tool speed (200, 300, 400, and 500 RPM) that affect the output responses namely hole dilation at inlet (HDin) and outlet (HDout). The optimal condition of input parameters was found to be V1/T1/S1 (100 V/10 μs/200 RPM). The voltage was observed to be the most affecting factor with a contribution of 90.95% while tool speed and pulse duration had a contribution of 5.91% and 1.48%, respectively. It was also found that the material removal mechanism was a complex phenomenon where sparking occurred both at end face and side surface of the tool. The deposition of pyrolytic carbon particles that helps in continuing the sparking was observed in the micrographic images obtained through field emission scanning electron microscope (FESEM). The burning of the matrix due to thermal effect and spalling was also evident which led to the removal of the material from the composite.

13 citations

Proceedings ArticleDOI
21 Jan 2019
TL;DR: This work proposes a corresponding automatic design solution which addresses all design objectives at once and employs an almost square-like layout and remains perfectly scalable while, at the same time, keeps the number of timesteps and utilized memristors close to the minimum.
Abstract: The identification of the memristor as fourth fundamental circuit element and, eventually, its fabrication in the HP labs provide new capabilities for in-memory computing. While there already exist sophisticated methods for realizing logic gates with memristors, mapping them to crossbar structures (which can easily be fabricated) still constitutes a challenging task. This is particularly the case since several (complementary) design objectives have to be satisfied, e.g. the design method has to be scalable, should yield designs requiring a low number of timesteps and utilized memristors, and a layout should result that is hardly skewed. However, all solutions proposed thus far only focus on one of these objectives and hardly address the other ones. Consequently, rather imperfect solutions are generated by state-of-the-art design methods for memristor-aided logic thus far. In this work, we propose a corresponding automatic design solution which addresses all these design objectives at once. To this end, a staircase structure is utilized which employs an almost square-like layout and remains perfectly scalable while, at the same time, keeps the number of timesteps and utilized memristors close to the minimum. Experimental evaluations confirm that the proposed approach indeed allows to satisfy all design objectives at once.

13 citations

Journal ArticleDOI
TL;DR: The conventional dynamic behavioral time-domain equations are modified and reported with adequate simulation responses with PMDC brushed motor operated at various PWM duty cycle and validated with satisfactory experimental results.
Abstract: The aim of this paper is to model a permanent-magnet direct current (PMDC) brushed motor considering the slotting effect and the effect of armature reaction and subsequent commutation phenomenon. These space-domain effects are mapped to time-domain equations of PMDC brushed motor by applying finite element approach (FEA) based geometrical modeling of armature. Conventionally, pulse width modulation (PWM) based approach is widely used to control PMDC brushed motor that essentially requires more precise time-domain model. Incorporating the slotting effect as a function of armature position, a reluctance model of PMDC brushed motor is framed. With the help of the reluctance model and by applying FEA over armature geometry, variation of various space-domain parameters are determined as a function of armature position in space that takes slotting effect into consideration. Furthermore, the effect of armature reaction or commutation is also taken into consideration as a function of both space-domain and time-domain parameters. Also incorporating the variation of space-domain parameters’ due to slotting effect and armature reaction, the conventional dynamic behavioral time-domain equations are modified and reported with adequate simulation responses with PMDC brushed motor operated at various PWM duty cycle. These modified time-domain equations based simulation responses are further validated with satisfactory experimental results.

13 citations


Authors

Showing all 517 results

NameH-indexPapersCitations
Sudip Misra485359846
Robert Wille434576881
Paul C. van Oorschot4115021478
Sourav Das301744026
Mukul Pradhan23531990
Bibhuti Bhusan Biswal201551413
Naba K. Nath20391813
Atanu Singha Roy19481071
Akhilendra Pratap Singh19991775
Abhishek Singh191071354
Vinay Kumar191301442
Dipankar Das19671904
Gayadhar Panda181231093
Gitish K. Dutta16261168
Kamalika Datta1569676
Network Information
Related Institutions (5)
Indian Institute of Technology Roorkee
21.4K papers, 419.9K citations

88% related

Indian Institute of Technology Delhi
26.9K papers, 503.8K citations

87% related

Indian Institute of Technology Kharagpur
38.6K papers, 714.5K citations

87% related

Indian Institute of Technology Madras
36.4K papers, 590.4K citations

86% related

Indian Institute of Technology Bombay
33.5K papers, 570.5K citations

86% related

Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20237
202236
2021191
2020220
2019184
2018155