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Institution

National Institute of Technology, Meghalaya

EducationShillong, India
About: National Institute of Technology, Meghalaya is a education organization based out in Shillong, India. It is known for research contribution in the topics: Control theory & Electric power system. The organization has 503 authors who have published 1062 publications receiving 6818 citations. The organization is also known as: NIT Meghalaya & NITM.

Papers published on a yearly basis

Papers
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Journal ArticleDOI
TL;DR: In this article, the effect of adding fly ash as well as incorporating polyethylene terephthalate (PET) fibres in a concrete mix to mitigate the lower quality of recycled aggregates in concrete is presented.
Abstract: The recycling of concrete is an important means to a sustainable material flow. The limited reuse of recycled aggregates is due to the lower quality of concrete production. Various methods have been attempted to minimise the negative effect. In this paper, the effect of adding fly ash as well as incorporating polyethylene terephthalate (PET) fibres in a concrete mix to mitigate the lower quality of recycled aggregates in concrete is presented. The study consists of two stages: in stage 1 the effects on some of the fresh and hardened concrete properties were studied and the percentage replacement of the natural coarse aggregate (NCA) by the recycled coarse aggregate (RCA) was established. From a chosen percentage of 10%, 20%, 30%, 50% and 100%, we found that the 20% replacement (RCA20) did not seem to jeopardise the compressive strength and water absorption of RCA concrete. Experimental studies were further carried out in stage 2 on the improvement on the mechanical properties of RCA20 concrete by incorpor...

7 citations

Proceedings ArticleDOI
01 Jan 2020
TL;DR: An analysis of BLDC motor for different types of slot according to four different slot shape according to finite element method to help the manufacturer choose the suitable slot shape for the machine design.
Abstract: This paper presents an analysis of BLDC motor for different types of slot. Four different model of BLDC motor is designed using finite element method according to four different slot shape keeping the slot area as constant. Different performance parameters such as motor efficiency, electromagnetic torque, output power, flux density are analysed for all the four designs. All the analysis are carried out using Ansys finite element and RMxprt. It will be useful for the manufacturer to choose the suitable slot shape for the machine design.

7 citations

Proceedings ArticleDOI
01 Mar 2017
TL;DR: A dynamic reconfigurable implementation for high speed and low area AES has been developed on Digilent's Zed board and implements two pipelined versions of AES for reconfiguration, high speed version using modular pipelining, area efficient version using simpler pipeline.
Abstract: Dynamic partial reconfiguration is the ability of modern FPGA's to dynamically change some selected area(s) of the FPGA while rest of the design is running. This feature allows to reuse the same hardware for different applications. In this paper we have chosen various Advanced Encryption Standard (AES) key sizes, viz. 128-bit, 192-bit and 256-bit as parameter for reconfiguration. A dynamic reconfigurable implementation for high speed and low area AES has been developed on Digilent's Zed board (XC7z020CLG484-1). The proposed work implements two pipelined versions of AES for reconfiguration, (i) High speed version using modular pipelining, (ii) Area efficient version using simpler pipeline. Maximum operational frequencies of 389.25, 389.25 & 386.2 MHz have been achieved using modular pipelined approach, while 204.3, 203.7 & 146.5 MHz is obtained for simple pipelined approach corresponding to 128, 192 and 256-bit AES respectively. The obtained throughput ranges from 49.8 Gbps to 98.8 Gbps for modular pipeline, and from 26.15 to 39.11 Gbps for simple pipeline structure.

7 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed a barrier coverage algorithm, called MCDP, which considers the rechargeable solar-powered sensors and applies the Probability Sensing Model (PSM) aiming to maximize the surveillance quality while the perpetual network lifetime of WSNs can be achieved.
Abstract: Barrier coverage problem is an important issue in wireless sensor networks (WSNs). Many solutions have been proposed for constructing a defense barrier aiming to maximize the surveillance quality while prolonging the network lifetime. However, most of them assumed that the sensor nodes are battery powered without considering the rechargeable sensors. Though the energy conservation issue has been taken into account in most studies, the perpetual network lifetime is still impossible. In addition, most of existing works considered Boolean Sensing Model (BSM) which cannot reflect the physical features of sensing. This paper proposes a barrier coverage algorithm, called MCDP , which considers the rechargeable solar-powered sensors and applies the Probability Sensing Model (PSM) aiming to maximize the surveillance quality while the perpetual network lifetime of WSNs can be achieved. The MCDP algorithm first partitions the time line and monitoring region into several space time points and calculates the detection probability of each sensor to each space time point. Then the proposed MCDP algorithm schedules sensors staying in sensing state and recharging state in each time slot such that the weakest cooperative surveillance quality of the time-space point can be maximized. Experimental study shows that the proposed MCDP algorithm achieves better performance than existing work in terms of surveillance quality, stability of cooperative detection probability as well as fault tolerance.

7 citations

Proceedings ArticleDOI
04 Jan 2016
TL;DR: A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods using negative bit-line approach.
Abstract: A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.5V for the 0.120um2 high density 6T-SRAM. Read margin of the SRAM cell is recovered using a compensated under driven word line scheme. Write assist is realized using negative bit-line approach. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation. Required word line under drive is 90mV to ensure correct read operation. For write assist, the undershoot requirement is 114mV. We could achieve a performance of 1.2MHz at 0.5V and 40MHz at 0.6V for a 288Kb capacity SRAM with 2K words of 144bits width. The area overhead of the read and write assist scheme is 1.0 percent and 2.5 percent respectively.

7 citations


Authors

Showing all 517 results

NameH-indexPapersCitations
Sudip Misra485359846
Robert Wille434576881
Paul C. van Oorschot4115021478
Sourav Das301744026
Mukul Pradhan23531990
Bibhuti Bhusan Biswal201551413
Naba K. Nath20391813
Atanu Singha Roy19481071
Akhilendra Pratap Singh19991775
Abhishek Singh191071354
Vinay Kumar191301442
Dipankar Das19671904
Gayadhar Panda181231093
Gitish K. Dutta16261168
Kamalika Datta1569676
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20237
202236
2021191
2020220
2019184
2018155