Showing papers by "NEC published in 1996"

Designated verifier proofs and their applications

Abstract: For many proofs of knowledge it is important that only the verifier designated by the confirmer can obtain any conviction of the correctness of the proof. A good example of such a situation is for undeniable signatures, where the confirmer of a signature wants to make sure that only the intended verifier(s) in fact can be convinced about the validity or invalidity of the signature. Generally, authentication of messages and off-the-record messages are in conflict with each other. We show how, using designation of verifiers, these notions can be combined, allowing authenticated but private conversations to take place. Our solution guarantees that only the specified verifier can be convinced by t,he proof, even if he shares all his secret information with entities that want to get convinced. Our solution is based on trap-door conim.itments [4], allowing the designated verifier to open up commitments in any way he wants. We demonstrate how a trap-door commitment scheme can be uscd to construct designated verifier proofs, both interactive and non-interactive. We examplify the verifier designation method for the confirmation protocol for undeniable signatures.

Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination

Abstract: Many applications in DSP, telecommunications, graphics, and control have computations that either involve a large number of multiplications of one variable with several constants, or can easily be transformed to that form. A proper optimization of this part of the computation, which we call the multiple constant multiplication (MCM) problem, often results in a significant improvement in several key design metrics, such as throughput, area, and power. However, until now little attention has been paid to the MCM problem. After defining the MCM problem, we introduce an effective problem formulation for solving it where first the minimum number of shifts that are needed is computed, and then the number of additions is minimized using common subexpression elimination. The algorithm for common subexpression elimination is based on an iterative pairwise matching heuristic. The power of the MCM approach is augmented by preprocessing the computation structure with a new scaling transformation that reduces the number of shifts and additions. An efficient branch and bound algorithm for applying the scaling transformation has also been developed. The flexibility of the MCM problem formulation enables the application of the iterative pairwise matching algorithm to several other important and common high level synthesis tasks, such as the minimization of the number of operations in constant matrix-vector multiplications, linear transforms, and single and multiple polynomial evaluations. All applications are illustrated by a number of benchmarks.

Giant magnetoresistance in Ti 2 Mn 2 O 7 with the pyrochlore structure

Abstract: MATERIALS exhibiting giant magnetoresistance (GMR) undergo a large change in electrical resistance in response to an applied magnetic field. This effect is of technological interest as it can be exploited for the sensitive detection of magnetic fields in magnetic memory devices. A range of compounds have now been found to exhibit intrinsic GMR—these are all perovskites based on manganese oxide1–4. Here we report the observation of GMR in Ti2Mn2O7, which has a pyrochlore structure and thus differs both structurally and electronically from perovskites. At 135 K the magnetoresistance ratio (the change in resistance) reaches–86% at 7 tesla, comparable to the GMR response of perovskite materials. In contrast to the hole-doped perovskites, the charge carriers in our material are electrons, as determined from measurements of the Hall coefficient. The discovery of GMR in a second class of material expands the options for optimizing magnetoresistive properties for specific technological applications.

Method for internet protocol switching over fast ATM cell transport

Abstract: A method for transporting Internet Protocols (IP's) over an Asynchronous Transfer Mode (ATM) network that exhibits the strengths of ATM, namely packet interleaving (using cell-based transport) with Quality of Service support for connection-oriented traffic (such as multiclass native ATM traffic and flows-based IP traffic using RSVP), while optimizing the connectionless requirements of existing IP traffic. Advantageously, both the IP protocol stack and ATM protocol stack operate as peers over ATM cell transport hardware. The method exploits an "implicit" signaling/control phase characteristic of IP traffic/protocols thereby minimizing setup. The implicit signaling phase is used to map a flow from a routed path to a switched path immediately upon transmission of a first packet. Similarly, particular packets may be immediately transported over the routed path even after establishment of the switched path. This mapping from the routed path to the switched path and vice versa is based upon the structure/semantics of the protocol driving the flow and not just the duration of the flow as done with prior-art methods. Consequently, while prior-art methods require cell-level counters to monitor activity (or lack thereof) for switching state, the method uses explicit control messages and soft-state at the IP level (as opposed to the cell level) to do the same. Advantageously, the method imposes no switching overhead as there is no coordination between neighboring nodes when a flow is moved from the routed path to the switched path.

Solid electrolytic capacitor with conductive polymer as solid electrolyte and method for fabricating the same

Abstract: The solid electrolytic capacitor disclosed has an electron donor organic compound layer of an organic compound provided between an oxide film as a dielectric and a conductive polymer layer and a conductive polymer layer as a solid electrolyte layer. In the step of forming the electron donor organic compound layer, the pellet on which the oxide film is formed, is caused to be exposed to vapor of the electron donor organic compound, and this enables the formation of a thin and uniform electron donor organic compound layer on the oxide film irrespective of the kind of electron donor organic compound. The pellet may alternatively be dipped in a solution of the electron donor organic compound. Where the dipping process uses silane coupling agent, aluminum coupling agent or titanium coupling agent, the thin and uniform electron donor organic compound layer can be formed by using alcohol solution or acidic solution of each coupling agent. The solid electrolytic capacitor having such a conductive polymer as a solid electrolyte is free from leakage current increase under high temperature condition.

Method and apparatus for cataloging and displaying e-mail using a classification rule preparing means and providing cataloging a piece of e-mail into multiple categories or classification types based on e-mail object information

Abstract: An electronic mail cataloging and retrieving system comprises an electronic mail communication unit, an electronic mail storage unit for storing electronic mails, a tray information storage unit for storing information on classification types used for classification of electronic mails and a format for relating electronic mails to said classification types, an electronic mail object storage unit for storing an electronic mail object related to each electronic mail stored in the electronic mail storage unit, a header information display control unit for showing header information and electronic mail attribute information on a prescribed electronic mail in the form of an at-a-glance guide, a tray display control unit showing tray information which shows that a prescribed electronic mail is classified into a prescribed classification type, and an electronic mail editing means for showing and editing the content of an electronic mail.

A comparative study of advanced MOSFET concepts

Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 /spl mu/m and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFET's parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed.

Source routing for connection-oriented network with repeated call attempts for satisfying user-specified QOS parameters

Abstract: In a connection-oriented network where ATM nodes are interconnected by links, periodically updated link status information of the network is stored in a database to indicate resource constraints of the network links Responsive to a connection request specifying multiple QOS parameters, a first path to a destination is selected and a first signaling message is transmitted containing routing data of the first path toward the destination if resource constraints of the first path satisfy all the specified QOS parameters If the transmission of the first signaling message is unsuccessful or the resource constraints of the first path do not satisfy all the specified QOS parameters, then a second path to the destination is selected according to contents of the database that correspond to one of the specified QOS parameters, and a second signaling message containing routing data of the second path is transmitted toward the destination

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Abstract: A 256-Mb SDRAM (245.7 mm/sup 2/) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current.

Phased array antenna with temperature compensating capability

Abstract: Generally, a variation of temperature at the installation site causes a phased array antenna radiation pattern to degrade. This paper describes the temperature characteristics of various components of the phased array antenna and degradations of the radiation pattern originating from temperature variations. It is effective to measure the phase distribution on the aperture and correct it, as the occasion demands, to prevent such degradations. Also, we propose a simple and effective algorithm for the measurement of the current distribution on the aperture, and present the evaluation test results of a phased array antenna with temperature compensation obtained by applying the algorithm.

Graphic user interface for managing a server system

Abstract: A graphical user interface provides a navigation model in the form of a hierarchical tree structure which is representative of a server system a user selected to manage. The hierarchical tree structure is populated or built to include a number of icons representative of different classes or categories of major components and their associated subcomponents contained in the selected server system and their logical relationships. In response to user icon selections, the navigation model expands and collapses the tree structure in a predetermined manner so as to enable the user to easily navigate through the different levels of components and subcomponents of the server with a minimum amount of information and determine status in addition to setting threshold values for items to be managed within the server system.

Focused ion beam applications to solid state devices

Abstract: The current state of focused ion beam (FIB) applications in relation to solid state devices is reviewed, and recent use of FIB technology for lithography, etching, deposition, and doping are described. Etching and deposition have become essential processes for failure analysis and for mask repair in silicon ULSL production. Furthermore, the FIB doping technique has been used to fabricate quantum effect devices.

A robust adaptive beamformer for microphone arrays with a blocking matrix using constrained adaptive filters

Abstract: This paper proposes a new robust adaptive beamformer applicable to microphone arrays. The proposed beamformer is a generalized sidelobe canceller (GSC) with a variable blocking matrix using coefficient-constrained adaptive digital filters (CCADFs). The CCADFs minimize leakage of target signal into the interference path of the GSC. Each coefficient of the CCADFs is constrained to avoid mistracking. The input signal to all the CCADFs is the output of a fixed beamformer. In a multiple-input canceller, leaky ADFs are used to decrease undesirable target-signal cancellation. The proposed beamformer can allow large look-direction error with almost no degradation in interference-reduction performance and can be implemented with a small number of microphones. The maximum allowable look-direction error can be specified by the user. Simulation results show that the proposed beamformer designed to allow about 20 degrees of look-direction error can suppress interference by more than 17 dB.

Infrared focal plane array incorporating silicon IC process compatible bolometer

Abstract: A 128/spl times/128 element bolometer infrared image sensor using thin film titanium is proposed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. By employing a metallic material like titanium and refining the CMOS readout circuit, it is possible to minimize 1/f noise. It is demonstrated that the use of low 1/f noise material will help increase bias current and improve the S/N ratio. Since the fabrication process is silicon-process compatible, costs can be kept low.

A framework for delivering multicast message in networks with mobile hosts

Abstract: To accommodate mobile hosts (MHs) within existing data networks, the static network is augmented with “mobile support stations” (MSSs) that communicate directly with MHs, usually via wireless links. Connectivity of the overall network changes dynamically as MHs connect to the static network fromdifferent “locations” (MSSs) at different times. Compared to their desktop counterparts, mobile hosts face a new set of constraints namely, low bandwidth of the wireless links, tight constraints on power consumption and a significantly lower computing capability. Thus, even without considering failures, integration of mobile computers within existing networks pose a new set of problems. In this paper, we look at the problems associated with delivering multicast messages to mobile hosts. First, we identify how a mobile host's ability to connect to different MSSs at different times, affects delivery of multicast messages and present schemes to deliver multicast messages to MHs from atleast-one location, from atmost-one location, and from exactly-one location. Next, we introduce ``multicast groups'' of mobile hosts wherein each multicast group is associated with a ``host view'', a set of MSSs representing the aggregate location information of the group. A host-view membership algorithmis then presented and combined with the multicast scheme for exactly-once delivery. As a result, to deliver a multicast message to a specified group, copies of the message need be propagated only to the MSSs in the group's host-view.

System for location multicasting and database management for mobile sessions in any computer subnetworks without using a home router of a home subnetwork

Abstract: In a computer network where each mobile host is assigned a subnetwork-independent logical identifier (L-ID), the mobile host acquires a subnetwork-dependent geographical identifier (G-ID) from an agent-existing subnetwork and sends the G-ID to the home subnetwork of the mobile host for location registration if a beacon received therefrom is a first one or different from a previous one or acquires a G-ID from an agentless subnetwork and sends the G-ID to the home subnetwork if no beacons are received. At intervals, a multicast packet is sent from the mobile host, containing the acquired G-ID to the agentless subnetwork. A similar multicast packet is received from a second mobile host and the G-ID contained therein is stored in a database corresponding to the L-ID of the second mobile host. When establishing a session, a data packet is sent from the mobile host to the network along with a G-ID corresponding to a L-ID of the data packet stored in the database. No G-ID is appended if the L-ID of the data packet has no corresponding identifier in the database. At the home subnetwork, a data packet destined to a mobile host of a subnetwork is encapsulated with the G-ID of the mobile host and routed to the subnetwork.

Semiconductor package stack module and method of producing the same

Abstract: In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.

Flash memory incorporating microcomputer having on-board writing function

Abstract: In a microcomputer comprising internal buses (AB, DB) , a serial communication interface (2), a flash memory (4) , a RAM (5), a ROM (6) for storing a writing program, an input/output port (1b), a CPU (7), and a mode control unit (3) for setting various operation modes and test modes in the microcomputer, a switching circuit (8) is connected between the ROM and the internal buses and between the input/output port and the internal buses. The mode control unit operates the switching circuit in an emulation test mode so that the ROM is deactivated and the input/output port is activated. Then, the CPU reads a program from the serial communication interface and writes the program into the flash memory in accordance with a writing program from the input/output port.

A GHz MOS adaptive pipeline technique using MOS current-mode logic

Abstract: This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

Content addressable memory of a simple construction capable of retrieving a variable word length data

Abstract: A content addressable memory system includes one retrieval sense amplifier provided in common with a plurality of memory words. A logic operation between a result of retrieval outputted from the sense amplifier and the result of a preceding retrieval stored in a one-bit working register provided for the same sense amplifier is carried out by a control gate also provided for the same sense amplifier, and the result of the logic operation is stored back in the same working register. A plurality of working registers may be provided for each control gate and sense amplifier. The content addressable memory system can retrieve a variable word length data and can be realized with a reduced circuit area.

Pulse-time modulated plasma discharge for highly selective, highly anisotropic and charge-free etching

Abstract: Highly selective, highly anisotropic, notch-free and charge-build-up damage-free polycrystalline silicon etching is performed by using electron cyclotron resonance plasma modulated at a pulse timing of a few tens of microseconds. A large quantity of negative ions is produced in the afterglow of the pulse-time modulated plasma. The decay times of electron density, electron temperature and sheath potential are considerably reduced, which is attributable to negative ion generation. Furthermore, the pulse-time modulated plasma reduces the time-averaged sheath potential. As a result of these effects, charged particles in the sheath are strongly modified from the continuous discharge, and they should improve selective etching in the pulsed ECR plasma and elimination of charge accumulation on the substrate.

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Abstract: This paper presents an efficient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach.

Workflow system for operating and managing jobs with predicting future progress of workflow job

Abstract: A workflow system includes workflow defining portion for defining workflow information necessary for operating workflow job to be realized by a sequence of unit businesses for which a plurality of workers are involved, workflow operating and managing portion for managing progress of the workflow job according to workflow information defined by the workflow defining means and urging execution of the unit job, individual information managing portion for managing individual information relating to each worker involving each unit job, and workflow predicting and evaluating projection for obtaining the workflow information defined by the workflow defining means, progress information indicative of progress of job of the workflow job managed by the workflow operating and managing means, and individual information managed by the individual information managing means, and for predicting future progress of the workflow job.

Semiconductor memory device with reduced chip area

Abstract: A semiconductor memory has memory cells arranged in a matrix to form a memory cell block. A word line is connected to each row of memory cells. The cell block has a pair of data lines, a row decoder circuit for activating one of the word lines and the pair of data lines, and a column decoder circuit for generating read and write select signals to selectively activate a desired column of memory cells and set that column to either a read or write mode. Each memory cell column has a pair of digit lines, a sense amplifier for amplifying differential data signals on the digit lines and read and write data transfer circuits for transferring differential read and write data signals to the digit lines in the read and write modes. The read data transfer circuit includes a pair of first MOS transistors connected to the data lines and activated with the read select signal, and a pair of second MOS transistors connected to the first MOS transistors in series. The gates of the second MOS transistors are connected to the digit lines. The second MOS transistors are operable to drive the data lines via the first MOS transistors by the differential read data signals in the read mode. The write data transfer circuit includes a pair of third MOS transistors provided between the data lines and the digit lines and activated with the write select signal.

Wireless ATM networks: architecture, system design and prototyping

Abstract: The concept of "wireless ATM", first proposed in 1992, is now being actively considered as a potential framework for next-generation wireless communication networks capable of supporting integrated, quality-of-service (QoS) based multimedia services. We outline the technological rationale for wireless ATM, present a system-level reference architecture, discuss key subsystem design issues, and summarize early prototyping results for a proof-of-concept system called "WATMnet". The reference architecture for wireless ATM consists of two major components: (a) a "radio access layer" for extension of ATM services over a wireless medium and (b) a "mobile ATM" infrastructure network capable of supporting terminal migration. Design considerations for both the radio access layer (e.g. physical layer, medium access control and data link control) and mobile ATM (e.g. handoff control, location management and routing/QoS control) are discussed, and key technical issues are identified in each case. An overview of experiences with the "WATMnet" system prototype developed at NEC USA's C&C Research Laboratories is given in conclusion.

System and method of eliminating quotation codes from an electronic mail message before synthesis

Abstract: In order to provide a practical E-mail reader for reading out E-mails phonetically enabling easy grasping of their contents by a user with its vocal output even when quotation codes or header information are included in the E-mails, a phonetic E-mail reader of the invention comprises a speech synthesizer (102) for converting text data into vocal data, quotation code storing means (105) for storing quotation codes used for indicating a quotation line inserted at a top of the quotation line, and quotation code elimination means (106) for detecting and eliminating a quotation code inserted at tops of quotation lines referring to the quotation code storing means (105) before supplying the quotation lines to the speech synthesizer (102).

Integrated electronic information system

Abstract: An electronic system using collectors, rosters, notifiers, and links provides a uniform system for communications, information management and human organization. Since the collectors have unique addresses, each collector belonging to a user can be used as a separate email inbox to provide a single user account with multiple email inboxes. Furthermore, collectors can have access control attributes to limit access to the collectors. The notifier provides a uniform location to view incoming new messages and documents. The links can be used to automatically transfer information between collectors as well as providing access authorization to collectors. For example, a link in subscription mode from a first collector to a second collector would automatically copy all documents placed in the second collector to the first collector. Similarly, if the same link were in forwarding mode, documents placed in the first collector are copied to the second collector. Rosters contain links to multiple collectors. A link to a roster is equivalent to a link to all the collectors linked in the roster. In addition sending a document to a roster is equivalent to sending a copy of the document to every collector linked in the roster.

Lead frame for use in a semiconductor device and method of manufacturing the semiconductor device using the same

Abstract: A distance between each two sides adjacent to a first portion X of the outer peripheral portion of an island portion 3 and the inner end of an inner lead portion 4 is set to d 1 while the distance between each two sides adjacent to a second portion Y, which is diagonal to the first portion X, and the inner end of the inner lead portion 4 is set to d 2 (