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Showing papers by "NEC published in 2006"


Journal ArticleDOI
TL;DR: The high efficiency of water-assisted CVD enabled the synthesis of nearly catalyst-free DWNT forests with a carbon purity of 99.95%, which could be templated into organized structures from lithographically patterned catalyst islands.
Abstract: We have succeeded in synthesizing vertically aligned doubled-walled carbon nanotube (DWNT) forests with heights of up to 2.2 mm by water-assisted chemical vapour deposition (CVD). We achieved 85% selectivity of DWNTs through a semi-empirical analysis of the relationships between the tube type and mean diameter and between the mean diameter and the film thickness of sputtered Fe, which was used here as a catalyst. Accordingly, catalysts were engineered for optimum DWNT selectivity by precisely controlling the Fe film thickness. The high efficiency of water-assisted CVD enabled the synthesis of nearly catalyst-free DWNT forests with a carbon purity of 99.95%, which could be templated into organized structures from lithographically patterned catalyst islands.

365 citations


Patent
Satoshi Matsui1
11 Sep 2006
TL;DR: In this article, a multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surfaces of chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment.
Abstract: The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.

240 citations


Journal ArticleDOI
J. Takeuchi1, Kenji Yamanishi1
TL;DR: This paper presents a unifying framework for dealing with outlier detection and change point detection, which is incrementally learned using an online discounting learning algorithm and compared with conventional methods to demonstrate its validity through simulation and experimental applications to incidents detection in network security.
Abstract: We are concerned with the issue of detecting outliers and change points from time series. In the area of data mining, there have been increased interest in these issues since outlier detection is related to fraud detection, rare event discovery, etc., while change-point detection is related to event/trend change detection, activity monitoring, etc. Although, in most previous work, outlier detection and change point detection have not been related explicitly, this paper presents a unifying framework for dealing with both of them. In this framework, a probabilistic model of time series is incrementally learned using an online discounting learning algorithm, which can track a drifting data source adaptively by forgetting out-of-date statistics gradually. A score for any given data is calculated in terms of its deviation from the learned model, with a higher score indicating a high possibility of being an outlier. By taking an average of the scores over a window of a fixed length and sliding the window, we may obtain a new time series consisting of moving-averaged scores. Change point detection is then reduced to the issue of detecting outliers in that time series. We compare the performance of our framework with those of conventional methods to demonstrate its validity through simulation and experimental applications to incidents detection in network security.

231 citations


Journal ArticleDOI
TL;DR: In this article, the authors developed high performance biomass-based plastics that consist of poly(lactic acid) (PLA) and kenaf fiber, which fixates CO2 efficiently.
Abstract: We have developed high-performance biomass-based plastics that consist of poly(lactic acid) (PLA) and kenaf fiber, which fixates CO2 efficiently. Adding this fiber to PLA greatly increases its heat resistance (distortion temperature under load) and modulus and also enhances its crystallization, so the ease of molding this material is improved. Eliminating the short particles from the kenaf fiber improves its effect on the impact strength. Kenaf fiber without the particles exhibits effects on these characteristics of PLA practically comparable to the effects of glass fiber. Furthermore, adding a flexibilizer (a copolymer of lactic acid and aliphatic polyester) to the composites improves their strength. These composites (PLA/kenaf fiber and PLA/kenaf fiber/flexibilizer) show good practical characteristics for housing materials of electronic products in comparison with petroleum-based plastics used in housing such as glass-fiber-reinforced acrylonitrile-butadien-styrene (ABS) resin. © 2006 Wiley Periodicals, Inc. J Appl Polym Sci 100: 618–624, 2006

209 citations


Patent
14 Dec 2006
TL;DR: In this paper, the authors proposed a radio communication system consisting of an RFID tag used for identification, a reader/writer for performing transmission and reception of information between the RFID tags by radio waves, and a plurality of reflecting plates in a space.
Abstract: It is to provide a radio communication system capable of performing highly reliable reading/writing communication even though the RFID tags face in the random directions. The radio communication system comprises an RFID tag used for identification, a reader/writer for performing transmission and reception of information between the RFID tag by radio waves, and a plurality of reflecting plates in a space where a plurality of RFID tags are accumulated. The reflecting plates direct traveling direction of the radio wave irradiated from the reader/writer towards the RFID tags. A part of the radio waves irradiated from an antenna of the reader/writer is directed to travel three-dimensionally towards the space by the effect of the reflecting plates. Moreover, the radio waves traveling in the same direction among the reflected radio waves by the plurality of reflecting plates together allow attenuation caused due to distance to be reduced extremely.

183 citations



Patent
09 Jun 2006
TL;DR: In this article, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles).
Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

164 citations


Journal ArticleDOI
TL;DR: In this article, a Si photonic wire waveguide was used for constructing various optical devices that are extremely small because the waveguides can be bent with extremely small curvatures of less than a few micrometers of bending radius.
Abstract: Si photonic wire waveguides are attractive for constructing various optical devices that are extremely small because the waveguides can be bent with extremely small curvatures of less than a few micrometers of bending radius. We have fabricated optical directional couplers with the waveguides and demonstrated their fundamental characteristics. Their coupling length was extremely short, several micrometers, because of strong optical coupling between the waveguide cores. We have also demonstrated wavelength-demultiplexing functions for these devices with a long coupled waveguide. Optical outputs from a device with a 100-mum-long coupled waveguide changed reciprocally with a 20-nm wavelength spacing between the parallel and cross ports. We also demonstrated the operation of ultrasmall optical add-drop multiplexers (OADMs) with Bragg grating reflectors made up of the waveguides. The dropping wavelength bandwidth of the OADMs was less than 0.7 nm, and these dropping wavelengths could be precisely designed by adjusting the grating period. Using the Si photonic wire waveguide, we have also demonstrated thermo-optic switches. Metal thin-film heaters were evaporated onto the branch of a Mach-Zehnder interferometer that incorporated the waveguide to achieve switching operations by thermo-optic effects. In these switching operations, we observed more than 30 dB of extinction ratio, less than 90 mW of switching power, and less than 100 mus of switching speed

156 citations


Patent
Yihong Gong1, Xin Liu1
18 Aug 2006
TL;DR: In this paper, the singular value decomposition (SVDC) is used for video segmentation, classification, and summarization based on a metric to measure the amount of information contained in each video shot of the input video sequence.
Abstract: In a technique for video segmentation, classification and summarization based on the singular value decomposition, frames of the input video sequence are represented by vectors composed of concatenated histograms descriptive of the spatial distributions of colors within the video frames. The singular value decomposition maps these vectors into a refined feature space. In the refined feature space produced by the singular value decomposition, the invention uses a metric to measure the amount of information contained in each video shot of the input video sequence. The most static video shot is defined as an information unit, and the content value computed from this shot is used as a threshold to cluster the remaining frames. The clustered frames are displayed using a set of static keyframes or a summary video sequence. The video segmentation technique relies on the distance between the frames in the refined feature space to calculate the similarity between frames in the input video sequence. The input video sequence is segmented based on the values of the calculated similarities. Finally, average video attribute values in each segment are used in classifying the segments.

154 citations


Journal ArticleDOI
Yasuharu Okamoto1
TL;DR: In this paper, density functional calculations were done to examine the interface between graphene and a Pt13 or Au13 cluster, and the CO and H chemisorption energies on the metal clusters on graphene were calculated to clarify supportdependent reactivity.

152 citations


Proceedings Article
01 Jun 2006
TL;DR: In this article, a magnetic random access memory with current-induced domain wall (DW) motion (DW-motion MRAM) was proposed. But its potential of 0.1-mA and 2-ns writing with sufficient thermal stability was not analyzed.
Abstract: We have developed a new magnetic random access memory with current-induced domain wall (DW) motion (DW-motion MRAM). We confirmed its potential of 0.1-mA and 2-ns writing with sufficient thermal stability. The obtained properties indicate that this MRAM can replace conventional high-speed embedded memories.

Patent
25 Oct 2006
TL;DR: In this article, a group III nitride-type field effect transistor (FET) was proposed to reduce a leak current component by conduction of residual carriers in a buffer layer and achieves improvement in a breakdown voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics.
Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

Patent
Kenichi Miki1
16 Jun 2006
TL;DR: In this paper, a path control device that controls first and second paths for accessing a peripheral subsystem, includes a command substituting unit that substitutes a first reserve command that allows an access through the first path, with a second reserve command allowing both of accesses through both of the first and the second paths.
Abstract: A path control device that controls first and second paths for accessing a peripheral subsystem, includes a command substituting unit that substitutes a first reserve command that allows an access through the first path, with a second reserve command that allows both of accesses through both of the first path and the second path.

Journal ArticleDOI
TL;DR: In this paper, a symmetrical Mach?Zehnder (SMZ) type, ultra-small and ultra-fast all-optical switch and logic device is presented.
Abstract: Nano-photonic technologies of GaAs-based two-dimensional photonic crystal (2DPC) slab waveguides (WGs) and InAs-based quantum dots (QDs) are reviewed for a symmetrical Mach?Zehnder (SMZ) type, ultra-small and ultra-fast all-optical switch (PC-SMZ) and logic device. As the first phase, ultra-fast (~ps) and ultra-low energy (~100?fJ) switching has been demonstrated using a chip 600??m?300??m in size. The second phase is to create a PC-SMZ-based ultra-fast photonic logic switch with a latch function for a future ultra-fast photonic digital processor. One of the priority subjects is to establish a new design method, i.e., topology optimization (TO) method of 2DPC-WGs with wide/flat bandwidth, high transmittance and low reflectivity. Another one is to develop selective-area-grown, high-density and highly uniform InAs QDs with large optical nonlinearity (ONL) by using a metal-mask (MM) molecular beam epitaxy (MBE) growth method. Recent results regarding these two subjects encourage us to reach the final goal.

Patent
14 Mar 2006
TL;DR: In this article, a method for thin film formation that can form, at a low temperature, a good thin film having a good interfacial property between a silicon substrate and a silicon oxide film and having a low interfacial trap density is provided.
Abstract: A method for thin film formation that can form, at a low temperature, a good thin film having a good interfacial property between a silicon substrate and a silicon oxide film and having a low interfacial trap density is provided. The method for thin film formation comprises generating plasma within a vacuum vessel to generate an active species (radical) and forming a silicon oxide film on a silicon substrate using this active species and a material gas, wherein, in addition to the material gas, a nitrogen atom-containing gas is introduced into the vacuum vessel in its film forming space where the active species (radical) and the material gas come into contact with each other for the first time and are reacted with each other to form a silicon film on the silicon substrate, and wherein the flow rate of the nitrogen atom-containing gas during the formation of the silicon oxide film on the silicon substrate is regulated so as to be the maximum value at least at the time of the start of formation of the silicon film on the silicon substrate.


Proceedings ArticleDOI
Kota Iwamoto1, Eiji Kasutani1, Akio Yamada1
01 Oct 2006
TL;DR: A new image signature which is a set of local features is developed for a high-speed frame-by-frame matching of video sequences, improving both the precision and the recall by more than 30% compared with the conventional signature.
Abstract: This paper proposes an image signature robust to caption superimposition for video sequence identification. A new image signature which is a set of local features is developed for a high-speed frame-by-frame matching of video sequences. The signature of a frame is obtained by partitioning the image into blocks and extracting the local feature representing the dominant type of edge direction from each block. The similarity between the signatures is calculated by comparing the edge types of the corresponding blocks, and counting the number of the blocks having the same edge type. A weighting scheme based on the probability of caption superimposition for each block can be applied to the similarity calculation to improve the matching performance. The experimental results of the video sequence identification show that the proposed signature achieves precision of 99.65% and recall of 99.45%, improving both the precision and the recall by more than 30% compared with the conventional signature.

Patent
Fan Ruixue1, Chi-Yu Lu2
23 Jan 2006
TL;DR: In this article, a pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach, where cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells.
Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.

Patent
Tomohiro Nishiyama1, Masamoto Tago1
12 Sep 2006
TL;DR: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible as discussed by the authors.
Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Proceedings Article
Kiyoshi Takeuchi, T. Nagumo, Shinji Yokogawa1, Kiyotaka Imai1, Yoshihiro Hayashi 
01 Jun 2006
TL;DR: In this article, a single charge-based random fluctuation model suited for analyzing both random telegraph noise (RTN) and intrinsic channel transistors (UTB-SOI, FinFET etc) is proposed.
Abstract: A single-charge-based random fluctuation model suited for analyzing both random telegraph noise (RTN) and intrinsic channel transistors (UTB-SOI, FinFET etc) is proposed Combining a quantitative formula for the worst case V TH shift (ΔV TH ) with measured data of RTN amplitude distributions, it is shown that RTN should not be ignored for scaled SRAM design The model also shows that scaling of intrinsic channel FETs will be limited by the fluctuations caused by residual random charge, which rapidly increase in proportion to 1/LW

Proceedings ArticleDOI
18 Sep 2006
TL;DR: In this article, a 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of oneGb/s per channel.
Abstract: A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

Journal ArticleDOI
TL;DR: In this article, the structural correlation between two adjacent graphitic layers in double-wall carbon nanotubes (DWNTs) was systematically examined by using electron diffraction, and the chiral indices of individual DWNTs were accurately determined.
Abstract: Structural correlation between two adjacent graphitic layers in double-wall carbon nanotubes (DWNTs) was systematically examined by using electron diffraction. Chiral angles and tube diameters were carefully measured, and the chiral indices of individual DWNTs were accurately determined. As a result, it was found that the interlayer distances of DWNTs were widely distributed in the range between 0.34 and 0.38 nm. Chiralities of the inner and outer tubes tended to be distributed at higher chiral angles, approaching 30 deg., for the tubes with diameter D {approx}3 nm, the chiral angles were widely distributed, covering the chiral map entirely. Therefore, we consider that tubes with small diameters have a tendency to form armchair type. Correlation of chiralities between the inner and outer tubes was found to be random.

Journal ArticleDOI
TL;DR: In this paper, the capacity of poly(5a)-based cell reached the theoretical value (109 Ah · kg -1 ) of the polymer, while poly(1, 3, and 4) gave polymers insoluble in common organic solvents in 88-100% yields.
Abstract: 2,2,6,6-Tetramethylpiperidine 1-oxyl (TEMPO)-containing N-propargylamide HC≡CCH 2 NHCO+TEMFO (1), propargyl ester HC≡CCH 2 OCO-4-TEMPO (2), phenylacetylene derivative HC≡CC 6 H 3 -3,4-(CO 2 -4-TEMPO) 2 (3), and norbornene diester monomers, NB-2,3-exo, exo-(CH 2 OCO-4-TEMPO)2 (4), NB-2,3-endo,exo-(COO-4-TEMPO) 2 (5a), NB-2,3-endo,endo-(COO-4-TEMPO)2 (5b) (NB = norbornorbornene, TEMPO = 2,2,6,6-tetramethyl-l-piperidinyloxyl) were synthesized and polymerized with rhodium and ruthenium catalysts. Monomers 2, 5a, and 5b gave polymers with number-average molecular weights of 47000-185000 in 59-100% yields, while 1, 3, and 4 gave polymers insoluble in common organic solvents in 88-100% yields. The capacities of cells fabricated with poly(1), poly(2), and poly(3) were 67, 82, and 23 Ah · kg -1 based on the weight, respectively. The capacity of poly(5a)-based cell reached the theoretical value (109 Ah · kg -1 ) of the polymer.

Patent
Ueno Kazuyoshi1
10 Aug 2006
TL;DR: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on the semiconductor substrate (S 100 ) ; forming a barrier metal layer on the whole surface of the insulating films (S 102 ), and selectively forming a cap metal layer after the step of removing the copper layer by polishing as mentioned in this paper.
Abstract: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S 100 ) ; forming a barrier metal layer on the whole surface of the insulating film (S 102 ); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S 104 ); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S 106 ); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S 108 ); and flattening the cap metal layer by polishing (S 110 ).

Patent
30 Nov 2006
TL;DR: In this article, an inner wall oxide film and an SOI layer is used to etch the resist and trench mask, and the trench for full isolation is formed by applying CMP treatment which used the silicon nitride film as the polishing stopper.
Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.

Journal ArticleDOI
TL;DR: In this paper, a bow-tie shaped aperture surrounded by concentric periodic structures in a metal film was used for terahertz-wave near-field imaging with subwavelength resolution.
Abstract: We demonstrate the terahertz-wave near-field imaging with subwavelength resolution using a bow-tie shaped aperture surrounded by concentric periodic structures in a metal film. A subwavelength aperture with concentric periodic grooves, which are known as a bull’s eye structure, shows extremely large enhanced transmission beyond the diffraction limit caused by the resonant excitation of surface waves. Additionally, a bow-tie aperture exhibits extraordinary field enhancement at the sharp tips of the metal, which enhances the transmission and the subwavelength spatial resolution. We introduced a bow-tie aperture to the bull’s eye structure and achieved high spatial resolution (∼λ∕17) in the near-field region. The terahertz-wave near-field image of the subwavelength metal pattern (pattern width=20μm) was obtained for the wavelength of 207μm.

Patent
22 Nov 2006
TL;DR: In this article, a chip with a pad, a bump electrode formed on the pad, and a wire whose stitch bonding is made on the bump electrode was presented. But the condition was not satisfied: (modulus of elasticity/breaking strength per unit area) >= 400.
Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) >=400.

Patent
Yoichiro Kurita1
02 Feb 2006
TL;DR: In this article, a planar semiconductor device with electrodes on both surfaces is disclosed, where the end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes.
Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.


Journal ArticleDOI
TL;DR: In this paper, a delay and power monitoring scheme for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltageV/sub TH/ in active and standby modes is presented.
Abstract: This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.