NEC

About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.

An efficient group signature scheme from bilinear maps

Abstract: We propose a new group signature scheme which is secure if we assume the Decision Diffie-Hellman assumption, the q-Strong Diffie-Hellman assumption, and the existence of random oracles. The proposed scheme is the most efficient among the all previous group signature schemes in signature length and in computational complexity.

The XAFS beamline BL01B1 at SPring-8.

Abstract: aJASRI, SPring-& Mikazuki, Sayo-gun, Hyougo 679-5198, Japan, bRIKEN, SPring-& Kamigori, Ako-gun, Hyougo 6795198, Japan, CjAERI Kansai, SPring-& Mikazuki, Sayogun, Hyougo 679-5143, Japan, dlnstitute of Scientific and Industrial Reseach, Osaka University, Ibaraki, Osaka 5670047, Japan, eFaculty of Science, Okayama University, Okayama 700, Japan, tDepartment of Molecular Engineering, Kyoto University, Kyoto 606-5801, Japan, gFaculty of Science, Osaka University, Toyonaka, Osaka 560, Japan, "Fundamental Research Laboratry, NEC, Tsukuba, Ibaragi 305, Japan. Emaihurugat@springS.or.jp

Register transfer level power optimization with emphasis on glitch analysis and reduction

Abstract: We present design-for-low-power techniques for register-transfer level (RTL) controller/data path circuits. We analyze the generation and propagation of glitches in both the control and data path parts of the circuit. In data-flow intensive designs, glitching power is primarily due to the chaining of arithmetic functional units. In control-flow intensive designs, on the other hand, multiplexer networks and registers dominate the total circuit power consumption, and the control logic can generate a significant amount of glitches at its outputs, which in turn propagate through the data path to account for a large portion of the glitching power in the entire circuit. Our analysis also highlights the relationship between the propagation of glitches from control signals and the bit-level correlation between data signals. Based on the analysis, we develop techniques that attempt to reduce glitching power consumption by minimizing propagation of glitches in the RTL circuit. Our techniques include restructuring multiplexer networks (to enhance data correlations and eliminate glitchy control signals), clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. In addition, we present a procedure to automatically perform the well-known power-reduction technique of clock gating through an efficient structural analysis of the RTL circuit, while avoiding the introduction of glitches on the clock signals. Application of the proposed power optimization techniques to several RTL circuits shows significant power savings, with negligible area and delay overheads.

Dynamic updating of routing information for routing packets between LAN's connected to a plurality of routers via a public network

Abstract: Connected to different routers of a packet routing network through a public network and to local area networks (LAN's) and comprising a routing table keeping routing information for an optimum path between each pair of the LAN's, a local router comprises a protocol processor for periodically processing the routing information into a local routing information protocol (RIP) datum indicative of connection information to the LAN's connected to the local router and a comparator comparing the local RIP datum with stored information of an RIP memory to discard and to write in the memory as a current datum the local RIP datum if the local RIP datum is coincident and incoincident with the stored information, respectively. A public network interface sends the current datum towards the different routers. In the routing table, the routing information is dynamically updated in response to an incoming RIP datum received from any one of the different routers.

Programmable function block

Abstract: A programmable function block 20 comprises a logic block 21 including a full adder 31 and at least one preposition logic 32, and an input block 22 including programmable input switch units 40-1 through 40-9 for use in selectively switching a HIGH logic level signal, a LOW logic level signal, and a signal on interconnection lines 50. The preposition logic 32 comprises an exclusive OR circuit 32-1 and a multiplexer 32-2 and functions as various different logic circuits by means of setting some of the inputs thereof to a HIGH logic level or a LOW logic level. Thus, the logic block functions as various different logic circuits depending on the state of the inputs. In addition, the full adder provides fast arithmetic operation.