Institution
NEC
Company•Tokyo, Japan•
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.
Topics: Signal, Layer (electronics), Terminal (electronics), Base station, Transmission (telecommunications)
Papers published on a yearly basis
Papers
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NEC1
TL;DR: In this article, a method for forming a metal compound film includes alternate irradiation of an organometal compound and oxygen or nitrogen radicals to deposit monoatomic layers of the metal compound.
Abstract: A method for forming a metal compound film includes alternate irradiation of an organometal compound and oxygen or nitrogen radicals to deposit monoatomic layers of the metal compound. The organometal compound includes zirconium, hafnium, lanthanide compounds. The resultant film includes little residual carbon and has excellent film characteristic with respect to leakage current.
243 citations
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NEC1
TL;DR: A semiconductor memory device of present invention has a memory cell, a sense amplifier which amplifies data of the memory, first IO line connected to the sense amplifier, and second IO line which is connected to first IO via a switch as discussed by the authors.
Abstract: A semiconductor memory device of present invention has a memory cell, a sense amplifier which amplifies data of the memory cell, first IO line connected to the sense amplifier, and second IO line which is connected to first IO line through a switch, wherein the second IO line is arranged on the memory cell.
241 citations
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NEC1
TL;DR: In this article, a multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surfaces of chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment.
Abstract: The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.
240 citations
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NEC1
TL;DR: In this paper, a novel method for microwave power transistor load-pull characterization is presented, where both input and output ports of a test transistor are simultaneously driven by external signals at the same specified frequency.
Abstract: A novel method for microwave power transistor load-pull characterization is presented. The method provides an equivalent load-pull measurement technique without using an output impedance tuner. In this method, both input and output ports of a test transistor are simultaneously driven by external signals at the same specified frequency. Results of its application to a medium-power GaAs FET are given.
240 citations
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10 Sep 2018TL;DR: This work utilizes recurrent neural networks to learn time-aware representations of relation types which can be used in conjunction with existing latent factorization methods to incorporate temporal information.
Abstract: Research on link prediction in knowledge graphs has mainly focused on static multi-relational data In this work we consider temporal knowledge graphs where relations between entities may only hold for a time interval or a specific point in time In line with previous work on static knowledge graphs, we propose to address this problem by learning latent entity and relation type representations To incorporate temporal information, we utilize recurrent neural networks to learn time-aware representations of relation types which can be used in conjunction with existing latent factorization methods The proposed approach is shown to be robust to common challenges in real-world KGs: the sparsity and heterogeneity of temporal expressions Experiments show the benefits of our approach on four temporal KGs The data sets are available under a permissive BSD-3 license
240 citations
Authors
Showing all 33297 results
Name | H-index | Papers | Citations |
---|---|---|---|
Pulickel M. Ajayan | 176 | 1223 | 136241 |
Xiaodong Wang | 135 | 1573 | 117552 |
S. Shankar Sastry | 122 | 858 | 86155 |
Sumio Iijima | 106 | 633 | 101834 |
Thomas W. Ebbesen | 99 | 305 | 70789 |
Kishor S. Trivedi | 95 | 698 | 36816 |
Sharad Malik | 95 | 615 | 37258 |
Shigeo Ohno | 91 | 303 | 28104 |
Adrian Perrig | 89 | 374 | 53367 |
Jan M. Rabaey | 81 | 525 | 36523 |
C. Lee Giles | 80 | 536 | 25636 |
Edward A. Lee | 78 | 462 | 34620 |
Otto Zhou | 74 | 322 | 18968 |
Katsumi Kaneko | 74 | 581 | 28619 |
Guido Groeseneken | 73 | 1074 | 26977 |