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Institution

NEC

CompanyTokyo, Japan
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.


Papers
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Patent
06 Jan 2011
TL;DR: In this paper, a nonvolatile semiconductor memory device includes a memory cell array, a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time.
Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

219 citations

Patent
09 Nov 1999
TL;DR: In this article, a system and method for customized advertisement selection and delivery on the World Wide Web (WWW) upon the Internet is presented, where a user connects to a web site and is presented with an editorial page or a list of search results.
Abstract: A system and method for customized advertisement selection and delivery on the World Wide Web (WWW) upon the Internet. The advertising system has a database server which stores advertisements and their campaign information, and an advertisement server which generates electronic advertisements available to a client system. In the system, a customization process which customized the electronic advertisements to be delivered to each client system is performed. A user connects to a web site and is presented with an editorial page or a list of search results. The system inserts a customized advertisement into the page that matches the page content or search topic. No identifiable data is collected during the interaction with the user. Advertisers can specify display constraints for each advertisement. The system will adapt all unrestricted parameters in order to maximize the user's click-through probability.

218 citations

Patent
01 Dec 2005
TL;DR: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer as mentioned in this paper.
Abstract: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer.

217 citations

Patent
Kenta Yamada1
15 Jul 2008
TL;DR: In this article, the authors propose a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor.
Abstract: A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount.

217 citations

Journal ArticleDOI
TL;DR: In this article, experimental data, device simulation, and analytical modeling for device comparison are employed. But the comparison is limited to the case of MOSFETs with channel length of 0.1 /spl mu/m and below reported in industrial research.
Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 /spl mu/m and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFET's parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed.

216 citations


Authors

Showing all 33297 results

NameH-indexPapersCitations
Pulickel M. Ajayan1761223136241
Xiaodong Wang1351573117552
S. Shankar Sastry12285886155
Sumio Iijima106633101834
Thomas W. Ebbesen9930570789
Kishor S. Trivedi9569836816
Sharad Malik9561537258
Shigeo Ohno9130328104
Adrian Perrig8937453367
Jan M. Rabaey8152536523
C. Lee Giles8053625636
Edward A. Lee7846234620
Otto Zhou7432218968
Katsumi Kaneko7458128619
Guido Groeseneken73107426977
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20238
202220
2021234
2020518
2019952
20181,088