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Institution

NEC

CompanyTokyo, Japan
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors discuss the design and development of system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits.
Abstract: Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

153 citations

Patent
Kazuhiro Okanoue1, Osawa Tomoki1
15 Aug 1996
TL;DR: In this paper, the authors propose a system where each mobile host is assigned a subnetwork independent logical identifier (L-ID), and the mobile host acquires a sub-network-dependent geographical identifier (G-ID) from an agent-existing subnetwork and sends the G-ID to the home subnetwork for location registration.
Abstract: In a computer network where each mobile host is assigned a subnetwork-independent logical identifier (L-ID), the mobile host acquires a subnetwork-dependent geographical identifier (G-ID) from an agent-existing subnetwork and sends the G-ID to the home subnetwork of the mobile host for location registration if a beacon received therefrom is a first one or different from a previous one or acquires a G-ID from an agentless subnetwork and sends the G-ID to the home subnetwork if no beacons are received. At intervals, a multicast packet is sent from the mobile host, containing the acquired G-ID to the agentless subnetwork. A similar multicast packet is received from a second mobile host and the G-ID contained therein is stored in a database corresponding to the L-ID of the second mobile host. When establishing a session, a data packet is sent from the mobile host to the network along with a G-ID corresponding to a L-ID of the data packet stored in the database. No G-ID is appended if the L-ID of the data packet has no corresponding identifier in the database. At the home subnetwork, a data packet destined to a mobile host of a subnetwork is encapsulated with the G-ID of the mobile host and routed to the subnetwork.

153 citations

Journal ArticleDOI
01 Jan 1992
TL;DR: In this article, a 64 Mw*1 b/16 mw*4 b DRAM with 30-ns access time was reported, which uses a double-metal layer and 0.4-mu m CMOS technology.
Abstract: A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

153 citations

Proceedings ArticleDOI
26 Jun 2018
TL;DR: This paper describes Version 2.0 of the ASVspoof 2017 database which was released to correct data anomalies detected post-evaluation and contains as-yet unpublished meta-data which describes recording and playback devices and acoustic environments which support the analysis of replay detection performance and limits.
Abstract: The now-acknowledged vulnerabilities of automatic speaker verification (ASV) technology to spoofing attacks have spawned interests to develop so-called spoofing countermeasures. By providing common databases, protocols and metrics for their assessment, the ASVspoof initiative was born to spear-head research in this area. The first competitive ASVspoof challenge held in 2015 focused on the assessment of countermeasures to protect ASV technology from voice conversion and speech synthesis spoofing attacks. The second challenge switched focus to the consideration of replay spoofing attacks and countermeasures. This paper describes Version 2.0 of the ASVspoof 2017 database which was released to correct data anomalies detected post-evaluation. The paper contains as-yet unpublished meta-data which describes recording and playback devices and acoustic environments. These support the analysis of replay detection performance and limits. Also described are new results for the official ASVspoof baseline system which is based upon a constant Q cesptral coefficient frontend and a Gaussian mixture model backend. Reported are enhancements to the baseline system in the form of log-energy coefficients and cepstral mean and variance normalisation in addition to an alternative i-vector backend. The best results correspond to a 48% relative reduction in equal error rate when compared to the original baseline system.

153 citations

Journal ArticleDOI
T. Sasaki1, Mitsuhiro Kitamura1, Ikuo Mito1
TL;DR: In this article, a mask-patterned planar planar InP substrate is used to grow InGaAsP/InP layers on typically 2 μm wide open stripe regions between pairs of SiO 2 mask stripes.

153 citations


Authors

Showing all 33297 results

NameH-indexPapersCitations
Pulickel M. Ajayan1761223136241
Xiaodong Wang1351573117552
S. Shankar Sastry12285886155
Sumio Iijima106633101834
Thomas W. Ebbesen9930570789
Kishor S. Trivedi9569836816
Sharad Malik9561537258
Shigeo Ohno9130328104
Adrian Perrig8937453367
Jan M. Rabaey8152536523
C. Lee Giles8053625636
Edward A. Lee7846234620
Otto Zhou7432218968
Katsumi Kaneko7458128619
Guido Groeseneken73107426977
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20238
202220
2021234
2020518
2019952
20181,088