Institution
NEC
Company•Tokyo, Japan•
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.
Topics: Signal, Layer (electronics), Terminal (electronics), Base station, Transmission (telecommunications)
Papers published on a yearly basis
Papers
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NEC1
TL;DR: In this article, the authors present a system in which a plurality of wireless interface devices, each containing one or more flash memory devices, are interfaced to a server which may be connected in either a wireless or wired LAN by way of a radio link.
Abstract: A system in which a plurality of wireless interface devices, each containing one or more flash memory devices, are interfaced to a server which may be connected in either a wireless or wired LAN by way of a radio link. The system in accordance with the present invention, enables the flash or other type of memory devices in the plurality of wireless interface devices interfaced to the server to be updated over a radio link.
153 citations
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NEC1
TL;DR: In this paper, density functional calculations were done to examine the interface between graphene and a Pt13 or Au13 cluster, and the CO and H chemisorption energies on the metal clusters on graphene were calculated to clarify supportdependent reactivity.
152 citations
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NEC1
TL;DR: This paper describes an auction protocol which hides the bids of non-winners even from the bid-opening centers, and still makes it possible to publicly verify the validity of the winning bid, i.e. that it was the highest bid submitted.
Abstract: Many auction protocols using practical cryptographic means have successfully achieved capability of hiding the bids of each entity, but not the values of bids themselves. In this paper we describe an auction protocol which hides the bids of non-winners even from the bid-opening centers, and still makes it possible to publicly verify the validity of the winning bid, i.e. that it was the highest bid submitted. The first approach to such a protocol was made by Kikuchi et al in [KHT98]. However, several deficiencies have been pointed out regarding their protocol; for example, it is not well suited for handling tie bids.
152 citations
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NEC1
TL;DR: In this paper, a semiconductor device having an IC (Integrated Circuit) chip packaged on a circuit board, and a cap for hermetically sealing the chip is described, where the cap is bonded to the circuit board at the edges of an open end of the chip and the chip at the underside or bottom thereof.
Abstract: A semiconductor device having an IC (Integrated Circuit) chip packaged on a circuit board, and a cap for hermetically sealing the chip. The cap is bonded to the circuit board at the edges of an open end thereof and bonded to the chip at the underside or bottom thereof. To accurately position the chip on the circuit board, the circuit board is provided with a groove or a shoulder in a position where it faces the edges of the open end of the cap. After the chip has been positioned on the circuit board, the cap is bonded to the circuit board via the groove or the shoulder.
152 citations
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NEC1
TL;DR: In this article, a phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree, and increments or decrements the count value in accordance with the output of the phase detector.
Abstract: In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector. The up-down count value is supplied as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree.
152 citations
Authors
Showing all 33297 results
Name | H-index | Papers | Citations |
---|---|---|---|
Pulickel M. Ajayan | 176 | 1223 | 136241 |
Xiaodong Wang | 135 | 1573 | 117552 |
S. Shankar Sastry | 122 | 858 | 86155 |
Sumio Iijima | 106 | 633 | 101834 |
Thomas W. Ebbesen | 99 | 305 | 70789 |
Kishor S. Trivedi | 95 | 698 | 36816 |
Sharad Malik | 95 | 615 | 37258 |
Shigeo Ohno | 91 | 303 | 28104 |
Adrian Perrig | 89 | 374 | 53367 |
Jan M. Rabaey | 81 | 525 | 36523 |
C. Lee Giles | 80 | 536 | 25636 |
Edward A. Lee | 78 | 462 | 34620 |
Otto Zhou | 74 | 322 | 18968 |
Katsumi Kaneko | 74 | 581 | 28619 |
Guido Groeseneken | 73 | 1074 | 26977 |