NEC

About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

Abstract: This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

Low-current perpendicular domain wall motion cell for scalable high-speed MRAM

Abstract: We have developed a new magnetic random access memory with current-induced domain wall (DW) motion (DW-motion MRAM). We confirmed its potential of 0.1-mA and 2-ns writing with sufficient thermal stability. The obtained properties indicate that this MRAM can replace conventional high-speed embedded memories.

Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

A GHz MOS adaptive pipeline technique using MOS current-mode logic

Abstract: This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

Mechanism of the Effect of NiCo, Ni and Co Catalysts on the Yield of Single-Wall Carbon Nanotubes Formed by Pulsed Nd:YAG Laser Ablation

Abstract: We revealed that the yield of SWNTs formed by Nd:YAG laser ablation depends on the target composition with yields following the order CxNiyCoy > CxNiy ≫ CxCoz. The SWNT bundles in the web formed when using the CxNiyCoy target (web-CxNiyCoy) is thicker and longer than those in the web-CxNiy. The diameters of the SWNTs in the web-CxNiyCoy were larger and more uniform than those of the SWNTs in the web-CxNiy. The NiCo particles in the web-CxNiyCoy and the Ni particles in the web-CxNiy were nanometer sized and were embedded in the amorphous carbon flakes that were dispersed throughout the weblike deposits. Filmlike deposits were formed when using the CxCoz targets, and nanometer-sized Co particles in these deposits were localized within sub-millimeter-sized areas. Examination of the target surfaces revealed that Ni emits from the CxNiy target more efficiently than NiCo from the CxNiyCoy target or Co from the CxCoz target during the laser ablation. On the basis of these results, we provide an explanation of ho...