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Institution

NEC

CompanyTokyo, Japan
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.


Papers
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Proceedings ArticleDOI
01 Jun 1999
TL;DR: The contribution of this work is the development of a vector generation procedure targeting the observability-based statement coverage metric, and a novel technique to set up constraints based on the chosen coverage metric for vector generation.
Abstract: Validation of RTL circuits remains the primary bottleneck in improving design turnaround time, and simulation remains the primary methodology for validation. Simulation-based validation has suffered from a disconnect between the metrics used to measure the error coverage of a set of simulation vectors, and the vector generation process. This disconnect has resulted in the simulation of virtually endless streams of vectors which achieve enhanced error coverage only infrequently. Another drawback has been that most error coverage metrics proposed have either been too simplistic or too inefficient to compute. Recently, an effective observability-based statement coverage metric was proposed along with a fast companion procedure for evaluating it. The contribution of our work is the development of a vector generation procedure targeting the observability-based statement coverage metric. Our method uses repeated coverage computation to minimize the number of vectors generated. For vector generation, we propose a novel technique to set up constraints based on the chosen coverage metric. Once the system of interacting arithmetic and Boolean constraints has been set up, it can be solved using hybrid linear programming and Boolean satisfiability methods. We present heuristics to control the size of the constraint system that needs to be solved. We present experimental results which show the viability of automatically generating vectors using our approach for industrial RTL circuits. We envision our system being used during the design process, as well as during post-design debugging.

145 citations

Patent
Inoue Takeshi1, Osamu Ohnishi1, Nobuo Ohde1
30 May 1990
TL;DR: In this article, the low and high impedance thickness mode vibration portions are integrally laminated and each vibrator portion comprises electrode layers between which a piezoelectric layer polarized in the direction of thickness is interposed.
Abstract: Low and high impedance thickness mode vibration portions are integrally laminated. Each vibrator portion comprises electrode layers between which a piezoelectric layer polarized in the direction of thickness is interposed. In each vibrator portion, every other electrode layer is connected to respective common external terminals. These common external terminals are of either four-terminal construction consisting two pairs, one pair for the low impedance mode vibrator portion and the other pair for the high impedance thickness mode vibrator portion, or three-terminal construction in which one of each pair are united together into a common terminal. Difference between the impedances is set on difference in the number of electrode layers and/or on difference in dielectric constant between the piezoelectric layers.

145 citations

Patent
Isao Sasaki1, Koichi Iguchi
05 Mar 2003
TL;DR: In this article, a pixel having a drive transistor and a pixel display element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of the drive transistor, and a selection transistor connected between a signal line and the gate electrode, is turned on, and gradation pixel data is written in the holding capacitor from the signal line.
Abstract: An image display apparatus comprises a pixel having a drive transistor and a pixel display element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of the drive transistor, and a selection transistor connected between a signal line and the gate electrode of the drive transistor. When the selection transistor is turned on, gradation pixel data is written in the holding capacitor from the signal line. The charge of gradation pixel data written in the holding capacitor is discharged for a certain period through the drive transistor, thereafter the charge of the gradation pixel data stored in the holding capacitor is held by floating the gate electrode of the drive transistor.

144 citations

Journal ArticleDOI
TL;DR: In this paper, the internal dynamics of a related model system, consisting of a K-dimensional endohedral complex enclosed in a carbon nanocapsule, was investigated, where transitions between the two states can be induced by applying an electric field between the end caps.
Abstract: Thermal treatment is reported to convert finely dispersed diamond powder to multiwall carbon nanocapsules containing fullerenes such as ${\mathrm{C}}_{60}$. We investigate the internal dynamics of a related model system, consisting of a $\mathrm{K}@{\mathrm{C}}_{60}^{+}$ endohedral complex enclosed in a ${\mathrm{C}}_{480}$ nanocapsule. We show this to be a tunable two-level system, where transitions between the two states can be induced by applying an electric field between the ${\mathrm{C}}_{480}$ end caps, and discuss its potential application as a nonvolatile memory element.

144 citations

Proceedings ArticleDOI
18 Jun 2000
TL;DR: An IP forwarding table search engine architecture, VLMP (vertical logical operation with mask-encoded prefix-length), for routers with multi-gigabit/sec speed links is proposed and a newly developed search LSI in which the architecture is implemented.
Abstract: We propose an IP forwarding table search engine architecture, VLMP (vertical logical operation with mask-encoded prefix-length), for routers with multi-gigabit/sec speed links. We discuss the existing approaches and the requirements for search engines, and go on to propose VLMP search engine architecture that expands upon a content addressable memory (CAM) and can perform wire-speed packet processing of an OC-192 (9.6 Gb/s) link. In this architecture, prefixes can be stored in arbitrary order, while existing ternary CAMs require prefixes to be stored in the order of their lengths. Also presented is a newly developed search LSI in which the architecture is implemented.

144 citations


Authors

Showing all 33297 results

NameH-indexPapersCitations
Pulickel M. Ajayan1761223136241
Xiaodong Wang1351573117552
S. Shankar Sastry12285886155
Sumio Iijima106633101834
Thomas W. Ebbesen9930570789
Kishor S. Trivedi9569836816
Sharad Malik9561537258
Shigeo Ohno9130328104
Adrian Perrig8937453367
Jan M. Rabaey8152536523
C. Lee Giles8053625636
Edward A. Lee7846234620
Otto Zhou7432218968
Katsumi Kaneko7458128619
Guido Groeseneken73107426977
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20238
202220
2021234
2020518
2019952
20181,088