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Institution

NEC

CompanyTokyo, Japan
About: NEC is a company organization based out in Tokyo, Japan. It is known for research contribution in the topics: Signal & Layer (electronics). The organization has 33269 authors who have published 57670 publications receiving 835952 citations. The organization is also known as: NEC Corporation & NEC Electronics Corporation.


Papers
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Patent
Kosuke Tanabe1
16 Mar 2010
TL;DR: In this paper, the authors proposed an antenna device for omni-cell systems with a plurality of sector antennas disposed so that a maximum radial direction where radiation intensity of a radio wave becomes maximum is radially set.
Abstract: An object of the present invention is to provide an antenna device that exhibits, in wireless communication of an omni-cell system for simultaneously transmitting a plurality of data corresponding to one another, excellent cost performance, and can reduce antenna loss and prevent radio wave interference. This antenna device includes a plurality of sector antennas 11 disposed so that a maximum radial direction where radiation intensity of a radio wave becomes maximum is radially set. The plurality of sector antennas 11 simultaneously transmit a plurality of wireless signals corresponding to one another.

133 citations

Patent
Hirohito Watanabe1, Toru Tatsumi1
20 Mar 1991
TL;DR: In this paper, a method for fabricating polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode, is described, by depositing a polycrystaline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystine silicon.
Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.

133 citations

Journal ArticleDOI
TL;DR: In this article, a hybrid-integrated symmetric Mach-Zehnder all-optical switch was developed for demultiplexing of 168-Gb/s data pulses at a repetition rate of 10 GHz with this switch.
Abstract: We have developed a hybrid-integrated symmetric Mach-Zehnder all-optical switch and evaluated the demultiplexing of 168-Gb/s data pulses at a repetition rate of 10 GHz with this switch. A compact, stable device was realized by assembling semiconductor optical amplifiers as nonlinear waveguides on a planar lightwave circuit in a self-aligned manner. A 6.0-ps switching window needed for 168-Gb/s demultiplexing was provided by the push-pull operation of the symmetric Mach-Zehnder all-optical switch. Demultiplexed signal light showed a high extinction ratio of better than 18 dB. Error-free demultiplexing with a bit error rate of 10/sup -11/ was achieved.

133 citations

Book ChapterDOI
11 Nov 1997
TL;DR: New anonymous channels which allow less than a half of faulty centers are shown and a fault tolerant multivalued election scheme is obtained automatically.
Abstract: Previous anonymous channels, called MIX nets, do not work if one center stops. This paper shows new anonymous channels which allow less than a half of faulty centers. A fault tolerant multivalued election scheme is obtained automatically. A very efficient ZKIP for the centers is also presented.

133 citations

Proceedings ArticleDOI
03 Jan 2001
TL;DR: This paper presents high-level models of a few commonly used on-chip architectures, which take into account key architectural features, including their characteristic topologies and communication protocols, and presents an efficient methodology to study the performance of each architecture.
Abstract: The emergence of several communication architectures for system-on-chips provides designers with a variety of design alternatives. In addition, the need to customize the system architecture for a specific application or domain, makes it critical for a designer to be aware of (and to evaluate) the trade-offs involved in selecting an optimal system-level communication architecture. While it is generally known that different communication architectures may be better suited to serve the needs of different applications, very little work has been done on quantitatively comparing and characterizing their performance for different classes of on-chip communication traffic. In this paper, we present a detailed analysis of the performance of various system-on-chip communication architectures under different classes of on-chip communication traffic. We present high-level models of a few commonly used on-chip architectures, which take into account key architectural features, including their characteristic topologies and communication protocols. We present an efficient methodology to study the performance of each architecture, making use of (i) parameterized traffic generators, that help create a wide variety of on-chip communication traffic, and (ii) an implementation independent communication interface abstraction, to enable plug-and-play evaluation of alternative communication architectures. Our experiments show that the effectiveness of each architecture varies significantly, depending on the characteristics of the communication traffic (average communication rates of common architectures were seen to vary by as much as 409%). Additionally, they also demonstrate the criticality of judiciously selecting an on-chip communication architecture for a given application. We discuss the implications of our experiments, including the relative strengths and weaknesses of the considered architectures, the classes of traffic that each is well suited to, and requirements for system design tools and methodologies in order to support efficient communication architecture selection and customization.

133 citations


Authors

Showing all 33297 results

NameH-indexPapersCitations
Pulickel M. Ajayan1761223136241
Xiaodong Wang1351573117552
S. Shankar Sastry12285886155
Sumio Iijima106633101834
Thomas W. Ebbesen9930570789
Kishor S. Trivedi9569836816
Sharad Malik9561537258
Shigeo Ohno9130328104
Adrian Perrig8937453367
Jan M. Rabaey8152536523
C. Lee Giles8053625636
Edward A. Lee7846234620
Otto Zhou7432218968
Katsumi Kaneko7458128619
Guido Groeseneken73107426977
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20238
202220
2021234
2020518
2019952
20181,088