About: NXP Semiconductors is a company organization based out in Eindhoven, Netherlands. It is known for research contribution in the topics: CMOS & Amplifier. The organization has 4170 authors who have published 4468 publications receiving 65349 citations. The organization is also known as: NXP.
Papers published on a yearly basis
•07 Oct 2011
TL;DR: This book provides an introduction to random matrix theory and shows how it can be used to tackle a variety of problems in wireless communications, including performance analysis of CDMA, MIMO and multi-cell networks, as well as signal detection and estimation in cognitive radio networks.
Abstract: Blending theoretical results with practical applications, this book provides an introduction to random matrix theory and shows how it can be used to tackle a variety of problems in wireless communications The Stieltjes transform method, free probability theory, combinatoric approaches, deterministic equivalents and spectral analysis methods for statistical inference are all covered from a unique engineering perspective Detailed mathematical derivations are presented throughout, with thorough explanation of the key results and all fundamental lemmas required for the reader to derive similar calculus on their own These core theoretical concepts are then applied to a wide range of real-world problems in signal processing and wireless communications, including performance analysis of CDMA, MIMO and multi-cell networks, as well as signal detection and estimation in cognitive radio networks The rigorous yet intuitive style helps demonstrate to students and researchers alike how to choose the correct approach for obtaining mathematically accurate results
TL;DR: It is shown that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDs(V GS) relation at practical gain values.
Abstract: An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDS(VGS) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm2.
••02 Dec 2012
TL;DR: In this paper, a block cipher called PRINCE is proposed that allows encryption of data within one clock cycle with a very competitive chip area compared to known solutions. But it does not have the α-reflection property, which holds that decryption for one key corresponds to encryption with another key.
Abstract: This paper presents a block cipher that is optimized with respect to latency when implemented in hardware. Such ciphers are desirable for many future pervasive applications with real-time security needs. Our cipher, named PRINCE, allows encryption of data within one clock cycle with a very competitive chip area compared to known solutions. The fully unrolled fashion in which such algorithms need to be implemented calls for innovative design choices. The number of rounds must be moderate and rounds must have short delays in hardware. At the same time, the traditional need that a cipher has to be iterative with very similar round functions disappears, an observation that increases the design space for the algorithm. An important further requirement is that realizing decryption and encryption results in minimum additional costs. PRINCE is designed in such a way that the overhead for decryption on top of encryption is negligible. More precisely for our cipher it holds that decryption for one key corresponds to encryption with a related key. This property we refer to as α-reflection is of independent interest and we prove its soundness against generic attacks.
••26 Dec 2006
TL;DR: In this article, RFID tags based on organic transistors are described, discussing in detail the IC blocks used to build the logic and the radio, and a complete 64-bit transponder, the most complex organic RFID tag reported to date, operates at 125 kHz.
Abstract: RFID tags based on organic transistors are described, discussing in detail the IC blocks used to build the logic and the radio. Tags energized and read out at 13.56 MHz, de facto standard frequency for item-level identification, have been tested and enabled for the first time multiple-object identification, using different 6-bit codes. A complete 64-bit transponder, the most complex organic RFID tag reported to date, operates at 125 kHz and employs 1938 transistors
01 Jan 1994
TL;DR: In this article, a two-stage, compact, power-efficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges is presented, which is very suitable as a VLSI library cell.
Abstract: This paper presents a two-stage, compact, power-efficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm/sup 2/, it is very suitable as a VLSI library cell. The floating class-AB control is shifted into the summing circuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current source biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which provides a power-supply-independent quiescent current. Using the compact architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation have been realized. The opamps have, respectively, a bandwidth-to-supply-power ratio of 4 MHz/mW and 11 MHz/mW for a capacitive load of 10 pF. >
Showing all 4173 results
|Dago M. de Leeuw||83||327||33086|
|Johan H. Huijsing||51||308||9609|
|Erik Jan Marinissen||43||196||7283|
|Christoph F. Mecklenbrauker||39||328||6618|
|Matteo Sonza Reorda||32||295||4525|