Rajasthan Technical University

About: Rajasthan Technical University is a education organization based out in Kota, Rajasthan, India. It is known for research contribution in the topics: Photovoltaic system & PID controller. The organization has 716 authors who have published 1084 publications receiving 4530 citations. The organization is also known as: RTU.

Comparison of Analytical and Heuristic Techniques for Multiobjective Optimization in Power System

Abstract: Due to liberalization in the power market stake of the Distributed Generation (DG) in the power industries has increased radically. Integration of DG will result is the change in the operating conditions of the existing power system network. Due to this DG has drawn attention of utility providers, policy makers and, to effectively use the DG, several researchers also. Inclusion of DG in the existing power system may enhance its power transfer capacity, voltage profile, reliability and it can also reduce the overall system losses if installed in proper capacity and at proper place. Benefits of DG can be efficiently extracted only if an appropriate capacity of DG is introduced in the existing power system at appropriate place. This chapter proposes an analytical and heuristic approach suggesting the optimum size and location of type-1 and type-2 DG. The proposed method is implemented on the IEEE-13 bus radial distribution network (RDN) and result shows the validity of the proposed method.

A secure and robust color image watermarking using nature-inspired intelligence

Abstract: The security of multimedia information is a prime concern in the present digital world. As a remedy, a robust color image watermarking in the transform domain using artificial intelligence is reported in this article. A color host image is secured by embedding a color watermark by utilizing the singular value decomposition and discrete wavelet transform. The color watermark information is scrambled with a chaotic map to give an additional stage of protection to overcome the problem of illegal copying and alteration of digital data by unauthorized users. All three RGB color channels of host singular values are modified with principal components of respective RGB information of scrambled watermark image. Ownership of data is provided by extracting the watermark in the presence of a secret key used while embedding process. To overcome the trade-off between the imperceptibility and robustness of the proposed algorithm artificial bee colony is used to optimize the scaling factor. The implementation of the proposed algorithm is performed on the MATLAB tool to compute the performance against the intentional and non-intentional image processing attacks. Comparative analysis with other related watermarking algorithms proves the robust, secure, and invisible nature of the proposed watermarking scheme.

Model order reduction of MIMO system using differentiation method

Abstract: In this paper differentiation method is proposed for driving reduced order model (ROM) of Multi-input multi — output (MIMO) linear dynamic system. The proposed method is based on differentiation of polynomials numerator and denominators. The reduction procedure is very simple given better response when compared with other reduction techniques and original high order system. Also, the proposed method guarantees given stability of the reduced models of MIMO system if the original high order MIMO system is stable. The proposed approach of MIMO system order reduction model is illustrated with the help of an Two-input and Two-output (2×2) transfer function matrix and the results of MIMO transfer function matrix are compared with the recently published reduction modal order techniques.

Han–Carlson adder based high-speed Vedic multiplier for complex multiplication

Abstract: Critical role is played by multipliers in modern digital signal processing systems. The overall system is affected by multipliers in terms of speed and computational complexity. In this paper, a Han–Carlson adder (HCA) based high-speed Vedic multiplier is proposed. The proposed Vedic multiplier uses Urdhva–Tiryakbhyam sutra of Vedic multiplication. Han–Carlson adder is one of the parallel-prefix adders which provides high-speed to the proposed multiplier architecture. Proposed architecture of 64 × 64 bit Vedic multiplier is implemented using Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with conventional Vedic multipliers with different adders which show that the conventional multipliers is having larger time delay as compared to proposed multiplier. Furthermore, complex multiplication architectures, using three and four 32 × 32 bit proposed Vedic multipliers are also implemented. The results of these complex multiplication architectures are also compared with conventional Booth multiplier and Array multiplier based architectures which show that the complex multiplication using proposed architecture provides improved delay, low hardware (LUTs) and low complexity.

Integral Inequalities Associated with Gauss Hypergeometric Function Fractional Integral Operators

Abstract: In this paper, some new integral inequalities related to the bounded functions, involving hypergepmetric fractional integral operators, are established. Special cases of the main results are also pointed out.