Renesas Electronics

About: Renesas Electronics is a company organization based out in Santa Clara, California, United States. It is known for research contribution in the topics: Semiconductor device & Signal. The organization has 8967 authors who have published 9511 publications receiving 109701 citations. The organization is also known as: Renesas Electronics Corporation & Runesasu Erekutoronikusu Kabushiki Gaisha.

Layer thickness dependence of the current-induced effective field vector in Ta|CoFeB|MgO

Abstract: Current-induced effective magnetic fields can provide efficient ways of electrically manipulating the magnetization of ultrathin magnetic heterostructures. Two effects, known as the Rashba spin orbit field and the spin Hall spin torque, have been reported to be responsible for the generation of the effective field. However, a quantitative understanding of the effective field, including its direction with respect to the current flow, is lacking. Here we describe vector measurements of the current-induced effective field in Ta|CoFeB|MgO heterostructrures. The effective field exhibits a significant dependence on the Ta and CoFeB layer thicknesses. In particular, a 1 nm thickness variation of the Ta layer can change the magnitude of the effective field by nearly two orders of magnitude. Moreover, its sign changes when the Ta layer thickness is reduced, indicating that there are two competing effects contributing to it. Our results illustrate that the presence of atomically thin metals can profoundly change the landscape for controlling magnetic moments in magnetic heterostructures electrically.

Semiconductor memory device

Abstract: PROBLEM TO BE SOLVED: To enable mixed mounting with a highly efficient electrical body capacitative element and a highly efficient logic circuit, by forming a dielectrics capacitative element of perovskite structure at low temperature, as well as by suppressing characteristic fluctuation and characteristics degradation of an integrated circuit. SOLUTION: In Pb-based perovskite dielectrics capacitative element, a mixing layer is so constituted that Ru is diffused in an LaNiO 3 -based film in order to raise adhesiveness of an Ru-based layer to the interface of the LaNiO 3 -based film, using lower electrodes wherein perovskite type conductivity oxide LaNiO 3 and Ru which is noble metal are laminated, and moreover the orientation degree of Ru (002) is 90% or more, and LaNiO 3 has a preference orientation degree (100), so that the orientation and grain size of a PZT film are controlled. Thus, the PZT film excellent in flatness and orientation is obtained. COPYRIGHT: (C)2005,JPO&NCIPI

Nonvolatile semiconductor memory

Abstract: Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.

Semiconductor device and a method of manufacturing the same

Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abstract: Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.