Showing papers by "Roma Tre University published in 1991"
07 Apr 1991
TL;DR: It is shown that due to the recursive mechanism, the copy generation is spatially distributed in the whole structure and is spread in time, which favorably affects the network's performance.
Abstract: A recursive multistage structure for multicast asynchronous transfer mode (ATM) switching is proposed, based on a connection network with a copying facility and external links connecting the outlets to the inlets. While the network generates only a few copies of an output multicast cell, the remaining are obtained by recycling the output copied cells to the corresponding inputs as many times as necessary. The basic features of a prototype binary multicast switch following the strategy are described. Its performance is also evaluated in terms of throughput and delay, via computer simulation. It is shown that due to the recursive mechanism, the copy generation is spatially distributed in the whole structure and is spread in time. This favorably affects the network's performance. >
36 citations
TL;DR: A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented.
Abstract: A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each state represents an operating chip configuration, and the state transitions take place in the presence of manufacturing defects. Results from the comparison of this method to a method for memory chip yield evaluation, a method for the M-out-of-N yield problem evaluation, and a method for the square grid chip yield evaluation are presented. >
19 citations
TL;DR: Nonlinear systems constituted by a zero-memory nonlinearity cascaded with linear filters can be identified by input-output cross correlation using a Gaussian input signal through a pair of complex invariance theorems.
Abstract: Nonlinear systems constituted by a zero-memory nonlinearity cascaded with linear filters can be identified by input-output cross correlation using a Gaussian input signal. The method is extended to complex systems through a pair of complex invariance theorems. The stated properties allow identifying the linear parts of systems characterized by magnitude/phase nonlinearities with the joint use of second- and third-order input-output moments. The method can be employed for a wide class of communication bandpass circuits when signals are represented by complex envelopes. >
19 citations
13 May 1991
TL;DR: An analysis is made of the latency time of an interconnection network based on a circuit switching technique for a hypercube multicomputer by using analytical and simulation models and it is shown that the drop strategy permits a higher amount of communication traffic within the network before reaching the network's saturation.
Abstract: An analysis is made of the latency time of an interconnection network based on a circuit switching technique for a hypercube multicomputer by using analytical and simulation models. To establish a path from a source to a destination node, some links have to be allocated. Links are serial resources, so when more communication requests request the same link, this contention has to be solved. Two main solution strategies are considered: the hold and the drop. It is shown that the drop strategy permits a higher amount of communication traffic within the network before reaching the network's saturation. However, such an approach requires a more complex communication router architecture. >
4 citations
TL;DR: It is shown that equivalent implementations of the ADA estimators actually require the same number of additions and comparisons as the RM estimator, so the computational costs of the two estimators are the same.
Abstract: Two fast estimators of correlation coefficients, namely the absolute difference average (ADA) and the relative magnitude (RM) correlators, have been proposed as well-suited for high correlation estimation. It is shown that equivalent implementations of the ADA estimators actually require the same number of additions and comparisons as the RM estimator. The computational costs of the two estimators are the same. >
3 citations
27 May 1991
TL;DR: An ASIC RNS implementation of a two-port constrained parallel adaptor for WDFs is presented and the speed performance can be improved through the use of parallel processors defined in terms of RNS, while the occupied area can be reduced realizing suitable isomorphism tables and reducing multiplier complexity to that of a sum.
Abstract: A method based on the residue number system (RNS) arithmetic is used. This method allows one to overcome these difficulties and to obtain high speed and low complexity WDF devices. In particular, the speed performance can be improved through the use of parallel processors defined in terms of RNS, while the occupied area can be reduced realizing suitable isomorphism tables and reducing multiplier complexity to that of a sum. In this paper, an ASIC RNS implementation of a two-port constrained parallel adaptor for WDFs is presented. >
1 citations
14 May 1991
TL;DR: A class of RNS filters is introduced which are not affected by coefficient and signal overflows in internal points and exhibits arithmetical features similar to those of conventional ones with larger wordlengths.
Abstract: The possibility of designing RNS (residue number system) recursive digital filters with reduced internal wordlength is considered. For this purpose, a class of RNS filters is introduced which are not affected by coefficient and signal overflows in internal points. The proposed filter architecture consist of two independent and parallel modular processors. A complete example of RNS fifth-order low-pass filters with 8-b wordlength is developed and compared with conventional fixed-point implementations. The proposed algorithm exhibits arithmetical features similar to those of conventional ones with larger wordlengths. This result is very promising in view of the development of ASIC architectures. >
15 Apr 1991
TL;DR: An innovative method for the 'apparent' yield evaluation is presented, which permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy.
Abstract: An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values. >