Showing papers by "Samsung published in 1988"
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30 Dec 1988
TL;DR: In this paper, an electrically erasable programmable semiconductor memory array for high density including a plurality of column lines and reference lines perpendicular to the column lines, was presented, where the drain-source paths of the first or second transistor and the floating gate transistors in each memory string were connected in series.
Abstract: An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the floating gate transistors in the lower memory strings being respectively connected to first and second select lines, each other upper word lines, third and fourth select lines and each other lower word lines The drains of the first and second transistors are connected to the column line through a single contact hole; the other ends of the serial connections in the upper memory strings are connected to the reference line adjacent thereto; and means for connecting the other ends of the serial connections in the lower memory strings to the reference line adjacent thereto
41 citations
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30 Dec 1988TL;DR: In this paper, the authors propose a data output buffer that can precharge a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in the semiconductor chip.
Abstract: A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.
40 citations
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TL;DR: In this article, the authors show that the coherency strain due to lattice diffusion is the driving force for the liquid film and grain boundary migration in sintered Mo-Ni alloy.
27 citations
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15 Jun 1988TL;DR: An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described in this paper.
Abstract: An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle. The data transmission circuit is characterized in that each of the inverting stages can operate under the control of a block selecting clock signal regardless of the precharging voltages of the true and complement I/O bus lines.
27 citations
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30 Dec 1988TL;DR: In this paper, a power supply voltage control circuit capable of preventing the failure of memory cells used for a long period of time, without lowering a power input voltage, is disclosed.
Abstract: SRAM device having a power supply voltage control circuit capable of preventing the failure of memory cells used for a long period of time, without lowering a power supply voltage is disclosed. The SRAM device includes a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each coupled between a word line and each pair of bit lines, and a power supply regulating stage coupled to each memory cell, for decreasing a supply voltage delivered to each memory cell when an external power supply voltage exceeds a specified voltage level, and delivering the external power supply voltage to each memory cell when the external power supply voltage does not exceed the specified voltage level. If an external power supply voltage is lower than a voltage level Vc, the supply voltage is supplied as a power source of the memory cell. However, when the external power supply voltage exceeds the voltage level Vc, there is supplied a voltage of common power supply line lower than the power supply voltage by a threshold voltage of a MOS transistor.
25 citations
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TL;DR: In this article, a circuit for generating back bias voltage for use in a semiconductor memory device is described, wherein the back bias voltages are clamped within a desired voltage level.
Abstract: A circuit for generating a back bias voltage for use in a semiconductor memory device is disclosed, wherein the back bias voltage is clamped within a desired voltage level. The circuit comprises an oscillator for generating a sequence of square waves having a specified frequency, a buffer adapted to be connected with the output of said oscillator and for buffering the output of said oscillator into the square waves having a level of a source supply voltage, a charge pump circuit for providing a back bias voltage by receiving the output of said buffer, and a clamping circuit adapted to be coupled in parallel between the output of said charge pump circuit and a ground level and for clamping within a specified range the back bias voltage being provided by said charge pump circuit in accordance with variations of said source supply voltage.
25 citations
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TL;DR: In this article, a complex modal control scheme was proposed to reduce the order of the system to be dealt with and minimise the required control energy and the transient magnitudes of the state.
23 citations
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26 Feb 1988Abstract: A digital automatic gain control system for maintaining a constant output level through attenuating or amplifying an input signal is disclosed. The system includes a gain control providing an output signal by amplifying or attenuating an input signal in a step mode in response to digital data of a data bus, a comparator deciding with a digital output whether or not said output signal is within a window reference voltage range, a stage preventing a malfunction due to noise by means of performing a counting operation upon receiving said digital output, a clock generating a clock pulse and dividing the frequency of the clock pulse, whereby there is provided a divided clock in case of performing an up counting operation and to the contrary there is provided the non-divided clock pulse in case of performing a down counting operation, and generating a reset clock delayed by a specified time interval from said clock, a latch adapted to receive and thereby latch an output of preventing stage malfunction, and reset clock and up/down counting and logic performing the up or down counting operation by receiving said clock and a latch signal.
23 citations
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16 Jun 1988TL;DR: In this article, a precharge circuit for static random access memory is described, where the first precharge step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step was performed via means for precharging more dominantly than the transistor pair in reaction to a second pulse generated via the address transition detection circuit.
Abstract: A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.
21 citations
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30 Dec 1988TL;DR: In this article, a mode selecting circuit for selecting a single operational mode in a semiconductor memory device having a plurality of operational modes is presented, where the mode selecting pad is bonded to the terminal of the power source so as to select a mode in the final assemblying stage of the manufacturing process, so that the process is simplified and the yield rate is increased.
Abstract: A mode selecting circuit for selecting a single operational mode in a semiconductor memory device having a plurality of operational modes. Instead of using an additional masking process, the present invention uses mode selecting pads, wherein a mode selecting pad is bonded to the terminal of the power source so as to select a mode in the final assemblying stage of the manufacturing process, so that the process is simplified and the yield rate is increased.
20 citations
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30 Nov 1988TL;DR: In this paper, a kimchi fermentor and control system using a KIMC curing sensor relates to a mass production of KIMCHI or naturally fermenting foods, in which the kIMC fermentor is provided with the kimi barrel having the heater and the cooler mounted therein, the agitator and the electric circuit based on the microprocessor.
Abstract: A kimchi fermentor and control system thereof using a kimchi curing sensor relates to a mass production of kimchi or naturally fermenting foods, in which the kimchi fermentor is provided with the kimchi barrel having the heater and the cooler mounted therein, the agitator and the electric circuit based on the microprocessor, otherwise the kimchi fermentor is adapted to a home refrigerator using the compressor and the fan in lieu of the cooler and agitator. Also in order to control the kimchi fermentor the microprocessor receives the signal having the control variables from the kimchi curing sensor and displays its operation mode according to the kimchi preparation method, the kimchi curing sensor is constructed to detect air bubbles and count the number of air bubbles so that the fermentation of kimchi is measured.
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04 Nov 1988TL;DR: In this article, a technique whereby digital video signals can be recorded or reproduced on or from a magnetic tape was disclosed, where the first controller converts analog video data into digital to store them in a memory, or reproduce said stored data by converting them into analog of real-time, a different input of the key is checked by the second controller to store said video signals into the tape.
Abstract: There is disclosed a technique whereby digital video signals can be recorded or reproduced on or from a magnetic tape. Using second controller to control a system such as a DAT recorder employing a digital signal processor, and first coutroller for converting said video signals into analog or digital, the video data are processed as in the conventional method of processing audio data according to the input of the mode selecting key. By the input of the key, the first controller converts analog video data into digital to store them in a memory, or reproduce said stored data by converting them into analog of real time, a different input of the key is checked by the second controller to store said video data into the tape. When storing said video data into the tape, the video signals are stored, imparted with synchronizing pulse to be distinguished from audio signals, and when reproducing said signals from the tape, the synchronizing pulse is detected to store only the video data into the memory, which data are reproduced by the first controller.
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09 Aug 1988TL;DR: In this article, the authors proposed to check the space between sound transmitter and sound receiver by means of electromagnetic waves, in particular light waves, for absence of obstacles, and/or not to use for the derivation of the distances those ultrasonic signals whose transit time and amplitude lie outside a given expectancy range.
Abstract: With the measurement of spatial movement of test points by means of ultrasonic signals, the problem exists that often interferences occur which may lead to distortion of test results It is proposed to check the space between sound transmitter and sound receiver by means of electromagnetic waves, in particular light waves, for absence of obstacles, and/or not to use for the derivation of the distances those ultrasonic signals whose transit time and/or amplitude lie outside a given expectancy range, but to discard them
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28 Jul 1988TL;DR: In this article, a multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit is presented, where one multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bits reference ladder for the reference voltage of the next comparison.
Abstract: A multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit. One multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bit reference ladder for the reference voltage of the next comparison. The other multiplexer is provided the reference voltages by accepting an analog input signal and the difference signal between an analog input signal and the output of a 4-bit digital analog converter. By using two multiplexers, only one analog digital converter is needed in this present device, so, the number of comparators is reduced. The multiplexer sends the digital signals compared with the most significant bit signal and the least significant bit signal, respectively, to a most significant output latch and a least significant output latch, respectively, so the 8-bit digital signal is obtained. The control unit is a logic circuit composed of flip-flops and gates, and provides clock signals for the sequential operation of the circuits, such as the operations of the multiplexers.
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18 Mar 1988TL;DR: An improved test pattern for monitoring variations of critical dimensions of patterns produced during the fabrication of semiconductor devices is disclosed in this paper, which allows the critical dimensions to be easily monitored by a microscope.
Abstract: An improved test pattern for monitoring variations of critical dimensions of patterns produced during the fabrication of semiconductor devices is disclosed. The test pattern which allows the critical dimensions to be easily monitored by a microscope, has a reference pattern including a reference line corresponding to one vertical edge of the reference pattern, said reference pattern formed flatly in a given layer below the present layer, a step shaped first pattern including a plurality of vertical indication step line segments corresponding to each vertical edge of the step and being formed flatly in the present layer, each extending line of said line segments being spaced by an equal horizontal interval and one of said line segments lying in the reference line, and a step shaped second pattern including a plurality of vertical indication step line segments corresponding to vertical edges of the step of the second pattern and being formed in separation from the first pattern in the present layer, each of said line segments of the second pattern being arranged on the extending line of each line segment of the first pattern.
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28 Dec 1988TL;DR: In this paper, the number of the mode-selecting clock generators is determined by the memory operating mode to be used, and a fuse is coupled with each generator when the corresponding mode selecting generator is selected and hence produces a mode selecting signal.
Abstract: In a selecting circuit for a memory operating mode, the circuit has a mode enable pulse generator which produces a short pulse for a mode enable pulse. A mode selecting clock generator which receives a mode enable pulse and selects a memory operating mode. The number of the mode selecting clock generator is determined by the number of memory operating mode to be used. A fuse, coupled with each of the mode selecting clock generators, is out when the corresponding mode selecting generator is selected and hence produces a mode selecting signal.
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27 Jul 1988TL;DR: In this article, a method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a poly-crystaline silicon layer for a resistor area over a silicon semiconductor substrate, a second step for growing a first thermal oxide layer having a specified depth over the poly-cell, ion-implanting with the nitrogen thereon, and growing a second thermal oxide on the ion-implanted layer, and a third step for forming a resistor pattern of the polycelline silicon with a photo etching method.
Abstract: Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.
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30 Dec 1988TL;DR: In this paper, a system for automatically compensating the transmitting (outgoing) signal level by detecting the receiving signal level received from a communication channel to a MODEM is presented, which includes a gain controller for controlling the output gain of the analog signal received from analog signal input terminal in accordance with gain control data.
Abstract: A system for automatically compensating the transmitting (outgoing) signal level by detecting the receiving (incoming) signal level received from a communication channel to MODEM Said system includes a gain controller for controlling the output gain of the analog signal received from analog signal input terminal in accordance with gain control data, hybrid means for amplifying the output of said gain controller, providing the amplified signal to transmit to a telephone line, and amplifying the analog signal received from the telephone line, receiving level sensing means for providing a plurality of receiving information data, said receiving information data teaching the level of the received signal, and a microprocessor unit for outputting the gain control data to said gain controller in response to the receiving information data and initial gain control data stored therein The gain control data increases or decreases according to the receiving information data provided to the microprocessor, if the level of the receiving signal to the MODEM is too high or too low, thereby controlling its transmitting gain with an optimum level according to the receiving level
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27 Dec 1988TL;DR: In this paper, a distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers.
Abstract: A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.
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26 Sep 1988TL;DR: In this paper, the authors used the arsenic implanted polycrystalline silicon for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current.
Abstract: Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor. The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current. Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously. Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.
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30 Dec 1988TL;DR: In this paper, an error-bit generating circuit was proposed for use in a nonvolatile semiconductor memory device, particularly in an EEPROM, which is capable of easily checking the deterioration of operational performance in an error checking correction device by intentionally writing bit-error data into a memory cell thereof.
Abstract: An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.
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27 Dec 1988TL;DR: In this paper, a method of forming low resistive contact to at least two pre-ohmic regions formed in a silicon substrate having a thick insulating layer thereon is described.
Abstract: A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.
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30 Sep 1988TL;DR: In this article, the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices is discussed.
Abstract: A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.
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16 Sep 1988TL;DR: In this article, a dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter.
Abstract: A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M 1 , M 2 composing of the inverter A, and to drains of MOS transistors M 3 , M 4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M 3 , M 4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M 4 and the signal is fed back.
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01 Jul 1988TL;DR: In this paper, an optical switching device for sensing an object is presented. But the device is not suitable for the detection of an object, and it requires the use of an oscillator, a light-emitting circuit for emitting a light pulse train corresponding to a pulse train from the oscillator to the object and a switching circuit for generating object detection logic signals.
Abstract: Optical switching device for sensing an object. The optical switching device includes an oscillator, an light-emitting circuit for emitting a light pulse train corresponding to a pulse train from the oscillator to the object, a light-receiving circuit for converting the light pulse train depending on the presence of the object into an electrical detection pulse train, a synchronous circuit for synchronizing the frequency of the detection pulse train with an adjustable frequency to provide a certain logic signal in synchronism, and a switching circuit for generating object detection logic signals in response to the logic signal from the synchronous circuit.
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13 Jul 1988TL;DR: In this article, a dynamic random access memory (DRAM) system is proposed, which comprises an array of storage cells in a well 64 on a substrate, a peripheral control circuit in a second well 62, 66 on the substrate, and means for differently biasing the wells.
Abstract: A dynamic random access memory (DRAM) comprises an array of storage cells in a well 64 on a substrate, a peripheral control circuit in a second well 62, 66 on the substrate, and means for differently biasing the wells. Complementary wells may carry CMOS peripheral control circuits. A ground potential may couple the wells carrying the storage arrays thereby to minimize voltage across the storage nodes for reducing array leakage and punch-through. An on-chip back-biasing generator may couple the complementary wells carrying the peripheral control circuits to improve signal margins and electrical performance. The array wells and the peripheral circuit wells are electrically isolated from one another so that back-bias generator noise does not interfere with the storage arrays. In this fashion, the storage nodes can be grounded advantageously while simultaneously basing the peripheral circuits.
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19 Feb 1988TL;DR: In this paper, a device and method for liquid-phase thin film epitaxial growth are disclosed wherein yield and quality of semiconductors in the fabrication sequences are improved, where an electric furnace which is disposed outside a quartz tube, a plurality of boats which are disposed within the quartz tube in accordance with a sort of melting liquids and an auxiliary heating devices are disposed around the boats with a power source independent from the electric furnace.
Abstract: A device and method for liquid-phase thin film epitaxial growth are disclosed wherein yield and quality of semiconductors in the fabrication sequences are improved. The device comprises an electric furnace which is disposed outside a quartz tube, a plurality of boats which are disposed within the quartz tube in accordance with a sort of melting liquids and a plurality of auxiliary heating devices are disposed around the boats with a power source independent from the electric furnace. According to this fabrication sequence, after heating the inner part of the quartz tube up to a first temperature level by supplying the power source to the electric furnace, the melting liquids are firstly melted down enough by means of selectively heating the auxiliary heating devices up to a second temperature level higher than the first temperature level, the substrates are then moved to be in contact with the melting liquids and an epitaxial growth layer is consequently formed through selectively reducing the temperature of the auxiliary heating devices to other levels different from the first and second level.
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14 Nov 1988TL;DR: In this paper, a push rod was installed inside the controlling shaft of a temperature controller, a locking pin for reciprocating upwardly and downwardly along the periphery of the pushing rod, and a locking bracket for catching the upper end of the locking pin.
Abstract: Means for locking the dial of a temperature controller according to the present invention comprises a push rod for locking the controller when pushed once and releasing the locking to return to the original position when pushed anew, said push rod being installed inside the controlling shaft of the controller, a locking pin for reciprocating upwardly and downwardly along the periphery of the controlling shaft by pushing of the push rod, and a locking bracket for catching the upper end of the locking pin to prevent the rotation of the controlling shaft when the locking pin reaching the upward position.
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30 Aug 1988TL;DR: In this article, a data output buffer circuit is provided for SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, which includes a drive output node from which output buffer provides output data.
Abstract: For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three states on the drive output node: a first and second output state, and a third high impedance state. None of the first, second, third, fourth, fifth, and sixth circuit requires use of a single pulse output signal externally provided to the data output buffer circuit. During transition from the first state to the second state, the drive output node passes through the third high impedance state.