Showing papers by "Samsung published in 1990"

Modular flat-screen television displays and modules and circuit drives therefor

Abstract: A modular flat-screen television display having a large area image can be made using an array of modules of easily manufacturable size and preferably removable. The image on each module extends to the edge of the module so that when placed in the array there is no substantial interruption in the television image since the distance between modules is the same as the distance between picture elements within the modules. Control and drive circuitry enable each module to be driven at the same time, thereby decreasing the time it takes to refresh the entire display. The modules contain picture elements which may be emissive, reflective or transmissive.

Digital multiplier employing CMOS transistors

Abstract: A digital multiplier for multiplying a binary N bit multiplicand by a binary N bit multiplier. The digital multiplier comprises a plurality of AND gates in which each digit of the mutliplicand is multiplied by each digit of the multiplier. The outputs of the AND gates represent partial products which are then arranged corresponding to each digit of the multiplier. The digital multiplier further comprises a plurality of 1's counters for receiving in parallel all partial products, except the least significant digit of the multiplier, and any carries propagated from an adjacent counter, and for counting the number of "1" in the resultant values. The 1's counters output the least significant bit as the final products, and propagate the remaining bits to the next 1's counter.

Concurrent engineering: decomposition and scheduling of design activities

Abstract: SUMMARY Design of complex products or large scale systems involves hundreds of resources (designers, analysts, computers, software systems, and procedures) and thousands of design activities. In this paper, a methodology is presented for decomposition of the design task into activities and modules. The methodology is based or clustering of design activities into groups that allow effective organization oi resources required in the design process. A knowledge-based approach is used for managing design activities. The system performs analysis aiming at exploring concurrency and reducing the design project makespan.

High voltage generating circuit for a semiconductor memory circuit

Abstract: There is provided a high voltage generating circuit including a circuit for sensing a voltage level of a high voltage for erasing and programming operations, a circuit for generating a given reference voltage, a circuit for comparing the sensed high voltage with the reference voltage, a circuit for applying or blocking a pump signal to a high voltage pump circuit according to the compared signal, a circuit for raising the voltage up to a given level under the control of the pump signal, and an EEPROM fuse circuit connected to the circuit for sensing the voltage level of the high voltage or the circuit for generating the given reference voltage and having stored data, whereby the voltage level of the high voltage finally output may be properly maintained and controlled according to the state of the stored data.

Simultaneous, multi-aspect ratio television display

Abstract: A system for simultaneously achieving the complete display of a plurality of subscreens of television video signals together with a main screen of television video signal without any overlapping (i.e., picture-out-of-picture; tiled displays), and thereby offer the pleasure to a viewer, of watching various types of a TV screen displays which are made up of various combinations of the subscreens and the main screen. The apparatus for multipicture regeneration uses an HDTV system and includes horizontal and vertical synchronizing counters, a logic control matrix part, a plurality of signal sources, a switching part, a scan direction data transfer part and an image processor. All of the selected subscreens and the main screen simultaneously displayed completely each with an aspect ratio of 3:4, on a single HDTV screen having an aspect ratio of 9:16.

Lap top computer with tilting mechanism consisting of a battery pack pivotally attached on a rear surface

Abstract: A lap top computer with a tilting mechanism attached is disclosed, and a battery pack is used for inclinedly supporting the computer body. The mechanism for connecting the computer body to the battery pack includes a pair of first guide members, a pair of second guide members, and a hinge. Each first guide member is provided with a guide slot, and the guide slot is formed in an elongate and arcuate shape concentrically around the shaft of the hinge. Each first guide member is further constituted such that one end thereof is fixedly installed within the rear portion of the computer body, and the other end thereof is projected through a hole of the rear portion of the computer body to the outside. One end of each second guide member is provided with a protuberance for being inserted into the guide slot of the first guide member, and the other end of each second guide member is fixedly installed within the battery pack.

Automatic paging telephone set and method for controlling thereof

Abstract: An automatic paging telephone set comprising first and second DTMF transmitters, a mode selector for selecting either a pager number recording mode, a paging mode, or a general communication mode, and a controller for controlling the telephone set according to the mode selected by the mode selector. When the telephone set is in the recording mode, the pager number data is stored into the memory of the controller. When the telephone set is in the paging mode, the controller stores the caller's telephone number into the memory thereof, and then transmts the pager number and the caller's telephone number to the paging system subscriber.

Semiconductor integrated circuit chip having an identification circuit therein

Abstract: A semiconductor integrated circuit chip has an identification circuit connected between a power voltage supply terminal and one of the input terminals of the chip. The identification circuity includes a voltage limiter to limit the input potential difference between the power voltage supply terminal and the input terminal to a predetermined voltage level. The identification circuit further includes an option device connected to the voltage limiter to provide identification information of the chip. According to the identification circuit, chip identification testing may be achieved with existing input/output and power supply terminals, thereby eliminating the need for extra test and diagnosis pins or additional identification equipment employed during testing.

Vehicle mounting apparatus of an automatic vehicle location system

Abstract: A vehicle mounting apparatus for an automatic vehicle location system having a omni-directional antenna, a transmitting and receiving switch, an oscillator frequency converters, a frequency-shift keying demodulator, post office committe standard associate group decoder, a pseudorandom noise signal generator, a phase-shift keying modulator, a transmitting signal generator, a power amplifier, and a power supplier. The vehicle mounting apparatus receives a referencing signal from a control center and transmits an answer signal relating to location of a vehicle to be located.

Overdischarge and overvoltage protection circuit for a battery in a portable and mobile communication system

Abstract: There is disclosed a circuit for protecting against overdischarge and overvoltage of a battery in a portable, mobile, and radio communication system including a low-power detection unit, a low-battery signal detection unit, a battery termination detection unit, a power supply controller, and a reference voltage converter.

Process for producing a stacked capacitor of a dram cell

Abstract: A stacked capacitor of the fin-like structure is provided wherein the plurality of polysilicon layers constituting the storage electrode are connected with each other in the sawtooth-like manner to overcome the structural instability of the fin-like structure. The polysilicon layers constituting the storage electrode are extended overlaying each other, so that the capacity of the capacitor in a highly integrated DRAM may be increased without increasing the area occupied by the capacitor.

Source voltage control circuit

Abstract: There is provided a source voltage control circuit including a reference voltage generating circuit with a negative feedback circuit, a source voltage level sensing circuit for increasing the internal source voltage when the external voltage exceeds a given voltage, a first differential amplifying circuit for active operation, and a second differential amplifying circuit for stand-by operation, whereby a stable internal source voltage is produced and the slope of the internal source voltage is readily adjusted when the external source voltage exceeds the given value. The first differential amplifying circuit receives the reference voltage and the internal source voltage, controlled by a first control signal and the output of the source voltage level sensing circuit. The second differential amplifying circuit receives the reference voltage and the internal source voltage, controlled by a second control signal.

Rechargeable battery controller

Abstract: A battery monitor system is disclosed comprising a microcontroller which monitors voltage inputs from a power adapter and a rechargeable battery. The power adapter includes a voltage source and a current source which outputs two current levels. A thermistor is thermally coupled to the battery, and the microcontroller receives voltage inputs from the battery and the thermistor. The microcontroller monitors and processes the voltage inputs to detect a predetermined voltage change corresponding to a change in the battery temperature and/or voltage level which indicates a fully charged battery. The level of the current which is provided to the battery from the current source is under the control of the microcontroller, such that the battery is maintained in a fully charged state.

Internal voltage converter in a semiconductor integrated circuit

Abstract: An internal voltage converter of a semiconductor integrated circuit according to the invention comprises an oscillator 1, a sub-circuit 10 incorporating a buffer 2 and a charge-pumping circuit 3 and a supply portion 4, a main circuit 20 incorporating a buffer 2' and a charge-pumping circuit 3' and a supply portion 4', and a detector 5. A set of voltage converter stages are arranged in parallel in order to be divided in operation, so that futile power consumption is reduced in the case of the provision of the quiescent supply and the stability of the internal supply source voltage is also improved. Application to semiconductor memory devices.

Static random access memory with redundancy

Abstract: A semiconductor memory device has normal memory blocks and redundant memory blocks for storing data therein. To elevate the redundancy efficiency, the memory device includes a number of normal block selectors for selecting the normal blocks, a number of redundant decoders for sensing a redundant mode on a basis of address signals provided thereto from an address buffer, a block selection decoder for generating a block selection signal by receiving an external address signal shaped, and a redundancy combining signal generator for generating a normal block selection signal and a redundant block selection signal by receiving output of the block selection decoder and output of the redundant decoder.

Apparatus for detecting coins and method thereof

Abstract: The present invention relates to an apparatus for detecting inserted coins and method thereof in units which are operated by inserting coins such as a vending machine, by using the configuration including the microcomputer for controlling the whole operation to detect the inserted coins, the quality, thickness and diameter detecting sensors for detecting the quality, the thickness and the diameter of the inserted coin and having the method comprising the steps of: counting the time required until the lastly positioned sensor senses the maximum value data after the firstly positioned sensor sensed the maximum value data; performing reset of the apparatus in case that the time required is more than the predetermined time; and discriminating the kinds of the inserted coins based on the quality, the thickness and the diameter maximum value data of the detected coins and the time required, thereby obtaining the advantage that the apparatus stops the operation and is reset when the insertion path is stopped up and that the kinds of the inseted coins are detected more correctly according to the quality, the thickness and the diameter of them.

Electrically page erasable and programmable read only memory

Abstract: An electrically page erasable and programmable read only memory device is an EEPROM device which is erasable page by page, and consists of flash-type floating gate transistors as the memory cells. The memory cell array of the device is divided by a plurality of pages, wherein each page comprises a plurality of bit lines, a plurality of common source lines, and a plurality of word lines. A plurality of erase selection circuits are arranged and correspond to the respective pages in order to erase the cells in a selected page, wherein each erase selection circuit comprises a passing transistor, a gate, a voltage stabilizing transistor, and an erasing line.

Video signal recording system enabling limited bandwidth recording and playback

Abstract: An improved video signal recording system for recording a full bandwidth video signal on a limited bandwidth medium is disclosed. The recording system includes an encoder, coupled to an input terminal, for adaptively processing a composite video signal in response to a motion representative signal, and producing two signals; a luminance signal, having attenuated high frequencies subsampled so as to be folded into a spectral hole in the low frequencies, and being bandwidth limited to the limited bandwidth of the recording medium; and a combined signal including a chrominance and a motion component. Luminance signal recording circuitry records the folded luminance signal on the medium and chrominance signal recording circuitry records the combined chrominance and motion signal on the medium. An improved video signal playback system for reproducing such a prerecorded video signal is also disclosed. The playback system consists of a luminance signal playback circuit for retrieving the prerecorded luminance signal from the medium, and chrominance signal playback circuit for retrieving the prerecorded combined chrominance and motion signals from the medium. A decorder extracts the motion signal and the chrominance signal from the combined chrominance and motion signal and an unfolding circuit extracts the luminance high frequencies from the prerecorded folded luminance signal and adaptively regenerates the full bandwidth luminance signal in response to the motion signal. This regenerated full bandwidth luminance signal is combined with the chrominance signal to reproduce the originally recorded composite video signal. A recording medium previously recorded by such a recording system is capable of being played back on a standard playback system without objectionably artifacts in the reproduced image.

Output buffer precharge circuit for DRAM

Abstract: An output buffer precharge circuit for DRAM (dynamic random access memory) cells includes a latch, control circuits, an output buffer, and a precharge pulse generating section. The circuit further includes a data transition signal genrating section consisting of MOS (metal-oxide semiconductor) transistors, latches connected to the MOS transistors, inverters and NAND gates for receiving the control precharge pulse from the precharge pulse generating section; and a precharge section consisting of MOS transistors, the gates of which receive the outputs of the data transition signal generating section. Noise can be decreased during the transition from the CMOS level to the TTL (transistor-transition-logic) level, and valid data are charged or discharged in advance so that processing speed can be increased.

Method for manufacturing a DRAM using selective epitaxial growth on a contact

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Device for securing peripheral equipment of computer

Abstract: A device for securing a peripheral equipment of computer is disclosed, and the device includes: a front plate of computer kept in an open state for receiving the peripheral equipment; a guide slot formed within the computer body; and flexible members installed on the opposite sides of the peripheral equipment. One end of the elastic member is elastically supported against the sides of the guide slot, and the other end of it is coupled with the front plate of the computer body. The flexible member is provided with a restraining portion and a clip portion, and the restraining portion is formed in an arcuate shape, while the clip portion includes a first, second and third bent portions. According to the present invention, no fastening tools are required, and therefore, the productivity is improved.

Adaptive associative memory comprising synapes of CMOS transistors

Abstract: An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit store the above mentioned stored vectors in the a binary 1 or 0; synapses of the label units couple the respective intersections between the input and output lines of the second amplifiers; and synapses of the vector units couple the intersections between the output lines of the first amplifiers and the input lines of the second amplifiers. According to the present invention, the outputs of the amplifiers are stabilized, so that stabilized operations can be obtained.

Signal delay circuit for minimizing the delay time dependence on power supply voltage variation

Abstract: A signal delay circuit includes a driving circuit for driving an output signal with a voltage swing voltage between a supply voltage and a ground voltage. The signal delay circuit further includes a varactor load which is coupled to the output signal and has a capacitance which increases according to the supply voltage within a variation range of the supply voltage. The varactor load keeps the delay characteristic of the signal propagation circuit independent of the change of the supply voltage, thereby ensuring high speed operation and improved reliability of the CMOS semiconductor integrated circuit.

Dust collector for an air cleaner

Abstract: An air cleaner comprises a dust collector of the positive corona using high voltage source, for example DC 7KV, to collect the dust particles in the air, a plurality of ionizing wires function as the heating wire, and the separate voltage source for the ionizing wire is a relatively lower voltage source, for example DC 24V, DC 48V, which may be overrided comparing with the voltage difference between the electrifying panel and the ionizing wire so as to prevent the ill influence on the electrifying function and the dust collecting function. Therefore, an air cleaner can combine air with heating a room so as to make air in the room comfortable.

Circuit for controlling generation of an acknowledge signal and a busy signal in a centronics compatible parallel interface

Abstract: There is disclosed a circuit for controlling the generation of a busy signal and an acknowledge signal properly to allow fast, accurate data communication between communication systems. The circuit includes: a Centronics interface cable for generating a strobe signal upon receiving data from a data communication device; a busy signal generator coupled to the Centronics interface cable, for generating a busy signal in response to the strobe signal and a busy signal generation control signal; a CPU coupled so as to control the entire system, for generating a received data processing completion signal in response to the busy signal; an acknowledge signal generator coupled to the Centronics interface cable, for generating an acknowledge signal in response to the state of the received data processing completion signal; and a counter for counting a predetermined clock responsive to the state of the received data processing completion signal to provide the acknowledge signal generator with an acknowledge signal generation control signal and to provide the busy signal generator with the busy signal.

Door hinge arrangement for opening the door at either side

Abstract: A door hinge arrangement for various home appliances such as a refrigerator, which permits opening of the door alternatively at either sie. The arrangement includes couples of hinge plates, receiving plates and locking pins engaged with the hinge plates, a connecting lever operationally connecting the locking pins to each other, and a pair of torsional springs for transmitting the movement of the locking pins to the connecting lever along guide grooves formed on the receiving plates. In this arrangement, the overall structure is simplified and opening of the door is carried out smoothly, as the hinge plates are connected directly to the connecting lever by the locking pins and the springs.

Circuit for saving battery for use in a radio paging receiver and method thereof

Abstract: A circuit for saving battery power in a radio paging receiver having a process for supplying first and second power saving signals indicative of first and second ON and OFF power signals. A first radio-frequency section converts the received radio-frequency signals upon reception of the first ON power signal; a second radio-frequency section then filters and demodulates the output signals from the first radio-frequency section to provide demodulated signals having a first voltage upon reception of the second ON power. A waveform shaper shapes the waveform of the demodulated signals to provide digital signals to the processor upon reception of the second ON power signal; and a switch enables and disables transmission of the first and second ON and OFF power signals from a power source to the first and second radio-frequency sections and the waveform shaper upon reception of the first and second power saving signals.

Control system for recording and reproducing a plurality of video signals

Abstract: The present invention is a video signal controller which can operate in one of two modes; play back mode and recording mode. Each camera has its own assigned display monitor and address code sequence. During operation of the video controller, each video signal is combined with its corresponding address signal that identifies from which camera the video signal is originally generated. The video signal and each address signal are then recorded via VTR onto a video tape. When the video signal controller is in play back mode, it extracts the synchronization signal and address signals from signals outputted by the VTR. The address signal and synchronization signals are used to locate and identify proper monitor to display its corresponding segment of signals from the VTR. Each monitor then plays back only those signals generated from its corresponding camera.

Plasma generating apparatus and method using modulation system

Abstract: The present invention provides a plasma generating method by using a modulation system in order to improve inner uniformity of plasma in plasma generating apparatus using the ECR plasma apparatus of another ECR system for performing an etching or deposition process. Unlike conventional fixed current systems, the embodiment disclosed transfers a high density ion portion to radiation form, thereby improving the uniformity of etching velocity or depositing velocity in wafers.

Method for manufacturing a semiconductor

Abstract: A method for manufacturing a BOX structured stack type capacitor of a semiconductor device is disclosed. The method comprises the steps of: defining an active region by forming a field oxide film on a semiconductor substrate of a first conductivity type; forming, on the active region, a gate electrode, a source region and a drain region of a transistor and forming a first conductive layer on a predetermined portion of the field oxide film and forming a first insulating layer on the gate electrode and the first conductive layer; forming a second insulating layer on the resultant structure; forming an opening in order to expose a portion of said source region and then depositing a second conductive layer on the entire surfaces of said second insulating layer and of the exposed substrate; forming a third insulating layer pattern of a saddle type by coating a third insulating layer on the second conductive layer; depositing a third conductive layer on the resultant structure; etching the third conductive layer disposed above the source region; removing said third insulating layer pattern and forming a first electrode pattern of a capacitor; and forming a dielectric film and a fourth conductive layer in turn on the resultant structure. In the method, the capacitance is increased by forming a storage node of a BOX structure and by using the inside and outside of the BOX structure as the effective area of the capacitor.