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Showing papers by "Samsung published in 1993"


Patent
22 Dec 1993
TL;DR: A nonvolatile memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cells.
Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage. Channel regions and source and drain junctions of cell units associated with memory transistors programmed to the other binary data are discharged to be programmed while those of cell units associated with nonprogrammed memory transistors are maintained to the program inhibition voltage to prevent programming.

194 citations


Patent
18 Feb 1993
TL;DR: In this article, a mobile detection system for detecting fire, gas leak, intruder, or other abnormal condition in a house or an office, and for alerting a central monitor, fire station, police station, or an occupant who is away from the house or office.
Abstract: A mobile detection system for detecting a fire, gas leak, intruder, or other abnormal condition in a house or an office, and for alerting a central monitor, fire station, police station, or an occupant who is away from the house or office. The mobile detection system comprises a self-propelled movable robot having sensors located thereon. A monitor receives signals from the robot and alerts an authorized user accordingly. An automatic communication control unit includes a telephone transmitting unit for automatically calling an appropriate party in response to a signal from the robot and transmits commands to the robot from an authorized calling party. A radio frequency remote controller for remotely controls the robot. The robot is specifically capable of navigating throughout a house or an office while using its sensors to detect abnormal conditions. In the event that an abnormal condition is detected, the robot initiates communication control unit to alert an appropriate party of the existing abnormal condition. Commands can be provided to the robot either directly through a keyboard on the robot itself, or remotely by way of the radio frequency remote controller or the automatic communication control unit.

161 citations


Patent
Kyeong-su Yu1
12 Oct 1993
TL;DR: In this article, an object tracking apparatus for an automatic zoom lens control in a video camera includes a memory for storing data for zoom track lines showing the relationship between the distance variation of a zoom lens and the distance variations of a focus lens while the distance of an object is kept constant.
Abstract: An object tracking apparatus for an automatic zoom lens control in a video camera includes a memory for storing data for zoom track lines showing the relationship between the distance variation of a zoom lens and the distance variation of a focus lens while the distance of an object is kept constant, a zoom encoder for producing a zoom position signal showing the zoom lens position, a microcomputer for detecting the variation amount of the zooming position, and a zoom motor for variably controlling the zoom lens position corresponding to the detected zoom speed. A corresponding method for automatic object tracking using a zoom lens is also described.

133 citations


Patent
Eung-Moon Yeon1, Young-Ho Lim1
08 Oct 1993
TL;DR: In this paper, a semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address, one for storing new data while the other latch circuit outputs its data to the page decoder for subsequent output.
Abstract: A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.

131 citations


Patent
30 Mar 1993
TL;DR: In this paper, a three-dimensional multichannel structure of a thin-film transistor gate with a 3D multi-channel structure is described, where the source/drain electrodes are formed so as to be spaced from and opposite to each other on a substrate, and the whole outer layer of each sub-semiconductive layer is used as channel regions.
Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

116 citations


Patent
20 Aug 1993
TL;DR: A relatively low power phase-shift-keyed (PSK) subcarrier encoding digital information is admixed with composite video signal, and the symbol rate is at a multiple of the scan line frequency.
Abstract: A relatively low power phase-shift-keyed (PSK) subcarrier encoding digital information is admixed with composite video signal. The PSK subcarrier is at an odd multiple of half the scan line frequency of the composite video signal, and the symbol rate is at a multiple of the scan line frequency. The PSK subcarrier modulates the amplitude of a suppressed carrier which is the same frequency as the video carrier for the composite video signal and preferably is in quadrature phasing therewith. To reduce evidence of the PSK subcarrier in television picture generated from that composite video signal, the PSK subcarrier is interrupted after each of periods of one frame duration and repeated in anti-phase during the next period of one frame duration. This also provides a basis for separating the PSK subcarrier from static luminance signal components by bandpass frame-comb filtering. Preferably, in the scan lines of consecutive pairs of scan lines, the PSK subcarrier is repeated with phase reversal of the subcarrier between scan lines, and the chroma subcarrier is repeated. This provides a basis for separating PSK subcarrier from chroma subcarrier by lowpass line-comb filtering.

114 citations


Patent
Gu-Sung Kim1
23 Jul 1993
TL;DR: In this paper, a process of manufacturing a semiconductor chip that has a connecting pad and is connected to a front side of a circuit board that had a conductive trace connected to the through-hole is described.
Abstract: A process of manufacturing a semiconductor chip that has a connecting pad and is connected to a front side of a circuit board that has a conductive trace connected to a through-hole. An insulating adhesive layer, which has a hole corresponding to the pad, is interposed between the chip and the board so that the pad, the hole in the insulating layer and the through-hole in the board are aligned. A conductive material is applied into the through-hole from the back side of the board so as to fill the through-hole and connect the pad to the trace. The conductive material may be applied using a sputtering method, a screening method, an electroplating method or an evaporating method. The back side of the board is polished to remove conductive material which may have been applied on the back side of the board outside the through-hole.

112 citations


Proceedings ArticleDOI
Dong-Il Kim1, Sungkwun Kim1
02 Oct 1993
TL;DR: In this article, a proportional, integral, and derivative (PID) type iterative learning controller is proposed for precise tracking control of industrial robots and computer numerical controller (CNC) machine tools performing repetitive tasks.
Abstract: A proportional, integral, and derivative (PID) type iterative learning controller is proposed for precise tracking control of industrial robots and computer numerical controller (CNC) machine tools performing repetitive tasks. The convergence of the output error by the proposed learning controller is guaranteed under a certain condition even when the system parameters are not known exactly and unknown external disturbances exist. As the proposed learning controller is repeatedly applied to the industrial robot or the CNC machine tool with the path-dependent repetitive task, the distance difference between the desired path and the actual tracked or machined path, which is one of the most significant factors in the evaluation of control performance, is progressively reduced. The experimental results demonstrate that the proposed learning controller can improve machining accuracy when the CNC machine tool performs repetitive machining tasks.

106 citations


Patent
Heon H. Moon1
29 Nov 1993
TL;DR: In this article, an encoder includes a direct current differential pulse code modulator for performing an adaptive frame/field processing, and a decoder has the similar constitution to that of the encoder and properly restores the DC value which is differentially modulated according to a predetermined mode, thereby decoding the restored signal into an original video signal.
Abstract: To encode a video signal by means of an interlace scanning method, a mode which generates the minimum number of bits with respect to four modes such as frame/field and inter/intra is selected and the video signal of the selected mode is encoded by adaptive frame/field processing. An encoder includes a direct current differential pulse code modulator for performing a direct current differential pulse code modulation only in the frame intramode and the field intramode among four paths to select a predetermined mode, and another direct current differential pulse code modulator for performing a direct current differential pulse code modulation according to the path of the selected mode by selecting one of the delayed signals after selecting the mode. A decoder has the similar constitution to that of the encoder and properly restores the DC value which is differentially pulse code modulated according to a predetermined mode, thereby decoding the restored signal into an original video signal.

103 citations


Patent
Chang-Hyun Yoo1
25 Mar 1993
TL;DR: In this paper, a self-driven robotic cleaning apparatus and method thereof which can reduce the production cost and shorten the cleaning time and thereby increase a cleaning efficiency is presented. But the method is not suitable for a large number of tasks.
Abstract: A self-driven robotic cleaning apparatus and method thereof which can reduce the production cost and shorten the cleaning time and thereby increase a cleaning efficiency, comprising: an infrared heat detecting circuit which senses infrared heat emitted form a human body and pet animals to thereby output a signal sensed from the same to the microprocessor; a front/rear operation motor driving circuit for receiving a driving signal outputted from the microprocessor to thereby rotate driving wheels in either a front or rear direction, a steering motor driving circuit for receiving the driving signal generated from the microprocessor to rotate the wheels and thereafter to change the direction of the wheels; an ultrasonic wave transmitting circuit for receiving an ultrasonic wave transmitting signal from the microprocessor to thereafter transmit the ultrasonic waves; an ultrasonic wave receiving circuit for receiving the ultrasonic waves transmitted from the ultrasonic wave transmitting circuit after the waves are reflected from an obstacle and thereafter for inputting a signal to the microprocessor indicating receipt of the ultrasonic waves by the ultrasonic wave receiving circuit; and a cleaning motor driving circuit for receiving the driving signal from the microprocessor to drive a cleaning motor and thereafter to perform a cleaning job.

93 citations


Patent
Goo-Man Park1
27 May 1993
TL;DR: In this article, the number of bits can be effectively fixed by placing inter-screen differential distortions and periodically varying in a preset period the positions of distortions when variable-length-encoding the respective pictures of the successive pictures with respect to a still image.
Abstract: An image compression and expansion methods for bit-rate fixation and the apparatus therefor in a video image apparatus which compresses the input image signal by performing a discrete cosine transform operation, quantizing, and variable-length-encoding the original image for each block respectively in order to enhance the compression efficiency. Thus, the number of bits can be effectively fixed by placing inter-screen differential distortions and periodically varying in a preset period the positions of distortions when variable-length-encoding the respective pictures of the successive pictures with respect to a still image.

Patent
21 Jul 1993
TL;DR: In this article, a disk recording medium includes a lead-in area, a program area and a leadout area, which can be accessed without an operating program or an application program.
Abstract: A disk recording medium includes a lead-in area, a program area and a lead-out area. The program area includes: a first track on which a plurality of data signals each of which has a different index from the others is loaded; a second track on which a plurality of programs is loaded, whereby the plurality of programs consists of the sequential combination of the indices of at least one data signal among the plurality of data signals and each program has a different index from the others; a third track on which a data index table comprising the indices of the respective data signals and initial address information is loaded; and a fourth track on which a program index table comprising the indices of the respective programs and initial address information is loaded. The lead-in area is loaded with a table of contents comprising the initial address information and a plurality of pointers each of which is different from the others and designates the respective tracks of the program area and the initial position of the lead-out area. Thus, larger programs can be contained on a single disk and can be accessed without an operating program or an application program.

Patent
18 Aug 1993
TL;DR: In this article, an EEPROM memory cell is formed on the first P-well and a first NMOS transistor is constructed on the second Pwell, where the impurity concentrations of the first and second N-wells are controlled in accordance with the characteristic of the MOS transistors to be formed.
Abstract: An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.

Patent
Lee Han-Gyo1
31 Aug 1993
TL;DR: In this article, an optional cassette can be used for an electrophotographic process engine, which occupies a minimum installation space and provides easy removal of jammed paper by using a pick up roller for picking up a paper.
Abstract: An optional cassette can be used for a electrophotographic process engine which occupies a minimum installation space and provides easy removal of jammed paper. A lower surface of the electrophotographic process engine is joined in steps with an upper surface of the optional cassette, and the the electrophotographic process engine comprises a second paper cassette and a second transmission passage formed vertically to a pull of paper in the second paper cassette. The optional cassette comprises an optional cassette module having a paper cassette slot for inserting a first paper cassette, and a pick up roller for picking up a paper form an uppermost paper of a paper pile in a position near the paper cassette slot and in the upper side of the option cassette module. A transmission unit, installed rotatably to the optional cassette with hinges under the second paper cassette 15, has a first transmission passage formed vertically to a pull of the first paper cassette and is connected with a second transmission passage.

Patent
Moon-Jong Song1
30 Dec 1993
TL;DR: In this article, an apparatus for use in the peripheral equipment of a computer reduces the needless consumption of power by controlling the supply of power and the operating state of the computer's peripheral equipment according to the equipment's operational state.
Abstract: An apparatus for use in the peripheral equipment of a computer reduces the needless consumption of power. Once it has been determined that the computer has not been used for a predetermined period of time, an operation control signal indicative of a specific control mode is supplied for controlling the supply of power to the computer's peripheral equipment and the computer's operating state. The operation of a power supply means for generating operating power to a computer's peripheral equipment is controlled in response to a detected control mode. Accordingly, energy is conserved by controlling the supply of power and the operating state of a computer's peripheral equipment according to the peripheral equipment's operational state.

Proceedings ArticleDOI
Seong-Won Lee1, Joonki Paik1
27 Apr 1993
TL;DR: The proposed adaptive version of a B-spline interpolation algorithm exhibits significant improvements in image quality compared with the conventional B- Spline type for algorithm, especially with high magnification ratio, such as four times or more.
Abstract: An adaptive version of a B-spline interpolation algorithm is proposed. Adaptivity is used in two different phases: (1) adaptive zero order interpolation is realized by considering directional edge information, and (2) adaptive length of the moving average filter in four directions is obtained by computing the local image statistics. The proposed algorithm exhibits significant improvements in image quality compared with the conventional B-spline type for algorithm, especially with high magnification ratio, such as four times or more. Another advantage of the proposed algorithm is its simplicity in both computation and implementations. >

Patent
27 Aug 1993
TL;DR: In this article, a storage electrode of a capacitor of a semiconductor memory device and a method for manufacturing the same are disclosed. And the capacitance is increased by using an etching endpoint detection layer and an HSG polysilicon layer.
Abstract: A storage electrode of a capacitor of a semiconductor memory device and a method for manufacturing the same are disclosed. A first electrode of the capacitor comprises a main electrode having a plurality of microtrenches and micropillars formed therein, an outer wall surrounding the microtrenches and micropillars, a granular silicon layer formed on an outer sidewall of the outer wall, and a column electrode supporting the main electrode and electrically connecting the main electrode to a source region of a transistor of the semiconductor device. The first electrode preferably has a horizontally fin-structured auxiliary electrode formed underneath the main electrode and electrically connected to the column electrode of the first electrode. The capacitor may be formed by using an etching end-point detection layer and an HSG polysilicon layer. The effective surface area of the storage electrode of a capacitor is increased to thereby obtain adequate cell capacitance. Also, uniform shapes of the storage electrodes are preferably obtained to thereby attain uniform cell capacitance.

Patent
10 Dec 1993
TL;DR: In this article, a manufacturing method for a semiconductor memory device including a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers.
Abstract: A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.

Patent
Je-Chang Jeong1
18 Jun 1993
TL;DR: In this paper, a method and apparatus for coding and decoding video data including a still image or active image on an intraframe basis is presented, where the coding system defines a search area composed of reconstructed data blocks and determines which one of the blocks within the search area has a pattern similar to a present data block that is in the process of being coded.
Abstract: A method and apparatus for coding and decoding video data including a still image or active image on an intraframe basis. The coding system defines a search area composed of reconstructed data blocks and determines which one of the blocks within the search area has a pattern similar to a present data block that is in the process of being coded. The system then computes the amount of displacement between the present data block and the reconstructed data block from the search area that has a pattern very similar to that of the present data block. The coded data is then stored in memory or transmitted. The decoding system implements a reverse process of the coding system to decode the coded data based on the displacement vector.

Patent
Sang-pil Sim1, Joo-Young Yun1, Chang-Kyu Hwang1, Jeong-gil Lee1, Chul-Ho Shin1, Won-Woo Lee1 
15 Jul 1993
TL;DR: In this paper, the double-cylindrical storage electrode of a capacitor of a semiconductor memory device was constructed from a single conductive layer, instead of a combination of layers as is conventionally known.
Abstract: A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known. Also, the storage electrode of the present invention has no sharp edges, so that leakage current can be minimized or avoided.

Patent
Park Doosik1
17 Dec 1993
TL;DR: A color image processor as discussed by the authors performs a first conversion on the output signal of a color image input device into the intermediate color space, and divides the region according to the deviation characteristics in the converted intermediate color spaces, and recorrects the color.
Abstract: A color image processor and method thereof which performs a first conversion on the output signal of a color image input device into the intermediate color space, and divides the region according to the deviation characteristics in the converted intermediate color space, and re-corrects the color, includes a first transform matrix, a region discriminator and a plurality of transform matrices.

Patent
Ha Dong-Inn1
30 Dec 1993
TL;DR: In this article, an extendable and retractable antenna installed on a body housing of a portable radio apparatus includes a helical antenna having an antenna cap protruding from a top portion of the body housing, a rod antenna extending through the antenna cap, and a feeder disposed at the bottom of the helical antennas.
Abstract: An extendable and retractable antenna installed on a body housing of a portable radio apparatus includes a helical antenna having an antenna cap protruding from a top portion of the body housing, a helical winding disposed within the antenna cap, a rod antenna extending through the antenna cap, and a feeder disposed at a bottom portion of the helical antenna. The helical antenna is operated when the antenna is retracted. The rod antenna is insulated from the helical antenna when retracted, and passes through the helical antenna to protrude from the body housing when extended. The feeder operates the rod antenna when the rod antenna is extended and operates the helical antenna when the rod antenna is retracted.

Patent
Jaewon Lee1
17 Dec 1993
TL;DR: In this article, a thin-film transistor was proposed to prevent the generation of a leakage current and to improve the operation stability of the transistor by using a reverse bias voltage suppression method.
Abstract: A thin film transistor wherein generation of a leakage current is prevented to improve the operation stability thereof and a method for manufacturing the same. A polysilicon layer is formed on an insulating layer. A gate insulating layer is formed on the polysilicon layer. A gate electrode having a barrier layer formed thereon is formed on the gate insulating layer. The sidewall surface portion of the gate electrode is anodic oxidized to form a metal oxide layer on the sidewall of the gate electrode. A lightly doped drain region having a lower impurity concentration than that of source and drain regions of the thin film transistor or an offset region wherein no impurity is doped is formed in a portion of the polysilicon layer under the metal oxide layer. The thin film transistor may be manufactured by a low temperature process, and leakage current is suppressed when a reverse bias voltage is applied. Therefore, the operation stability of the thin film transistor is improved.

Patent
Kangok Lee1
02 Mar 1993
TL;DR: In this paper, a silicon field emission emitter with thermal oxide film and a gate electrode is described. But the method for making the emitter has not been described, and it is not known how to construct the gate electrode.
Abstract: There is disclosed a silicon field emission emitter and a method for making a silicon field emission emitter which has a good electronic characteristic and a simplified making process. The silicon field emission emitter in accordance with the embodiment of the present invention includes a silicon substrate of high density, an insulating layer on the silicon substrate of high density, a cavity formed in the insulating layer, an emitter formed with the silicon substrate of high density in a body in the cavity, and a gate electrode formed on the insulating layer. The insulating layer is made of the thermal oxide film having the thickness of 4000 angstroms and the gate electrode coats the emitter tip.

Patent
16 Dec 1993
TL;DR: In this article, a variable advance instruction window is used for storing a group of instructions to be executed by the processor, where a new instruction is added to the variable advance instructions window when a location becomes available.
Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

Patent
Sang-In Lee1, Chang-Soo Park1
25 Jan 1993
TL;DR: In this article, a reactive spacer or layer is formed on the sidewall of the opening to improve the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature.
Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 μm in size and having an aspect ratio greater than 1.0, can be completely filled with Al, to thereby enhance the reliability of the wiring of a semiconductor device.

Patent
Seong W. An1
12 Feb 1993
TL;DR: In this paper, a microwave output stabilizing apparatus for a microwave oven comprises a rectifier circuit for rectifying power from an AC power supply into a constant DC voltage, an invertor circuit for generating a high frequency power supply by controlling the DC voltage at an intermittent output state, a high voltage transformer for stepping up the high-frequency power supply, and magnetron drive circuit for oscillating a magnetron.
Abstract: A microwave output stabilizing apparatus for a microwave oven comprises a rectifier circuit for rectifying power from an AC power supply into a constant DC voltage; an invertor circuit for generating a high frequency power supply by controlling the DC voltage at an intermittent output state; a high voltage transformer for stepping up the high frequency power supply; and magnetron drive circuit for rectifying the high frequency power supply and oscillating a magnetron. Also, an inverter control circuit detects the current flowing into the primary winding of the high voltage transformer, converts the detected current into a corresponding voltage, the corresponding voltage with a reference voltage, and controls the inverter circuit according to the results of the comparison. Further included are an anode current detecting circuit for detecting the anode current of the magnetron and converting the detected anode current into the corresponding voltage; and, a reference voltage adjusting circuit for evaluating the anode current and changing the reference voltage of the invertor control circuit in accordance with the results of the evaluation.

Patent
Sang-soo Kim1, In-sik Jang1, Dong-Gyu Kim1, Jun-ho Song1, Woon-Yong Park1 
01 Jun 1993
TL;DR: In this paper, an active matrix-type liquid crystal display is described having, for each pixel, a first electrode for of a storage capacitor that is connected to a scanning signal line.
Abstract: An active matrix-type liquid crystal display is described having, for each pixel, a first electrode for of a storage capacitor that is connected to a scanning signal line. The liquid crystal display can be repaired for disconnections and short inferiorities occurring in a crossing portion of scanning signal line. A redundancy correcting line connects the capacitor electrodes of adjacent pixels. Also described is a double scanning signal line. The embodiments using the redundant connecting line and double scanning signal line are both repairable using laser if imperfections exist. Thus, the disconnections and shorts in the crossing portion of wirings can be minimized.

Patent
Jae-Gu Roh1, Yong-Sik Seok1
05 Feb 1993
TL;DR: A column redundancy circuit for a DRAM memory device is presented in this article, which includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, and a column address decoder which are each programmed by means of a selected number of their fuses being blown, e.g., by use of a laser.
Abstract: A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective. The column redundancy circuit includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, a column address decoder which is programmed to generate a second output signal in response to receipt of both the first output signal and a column address signal corresponding to the defective column, and, a redundant column driver circuit which is responsive to the second output signal for activating a predetermined one of the redundant columns, to thereby repair the defective column. In a preferred embodiment, the block selection control circuit and the column address decoder each include a plurality of fuses and are each programmed by means of a selected one or more of their fuses being blown, e.g., by use of a laser.

Journal ArticleDOI
TL;DR: This paper uses a memory of size O(n log n) bits to store a Huffman code tree, where a is the number of symbols, and shows a design for I-bit symbols.
Abstract: In this paper, we present simple and area efficient VLSI architectures for Huffman coding, an industrial standard proposed by MPEG, JPEG, and others. We use a memory of size O(n log n) bits to store a Huffman code tree, where a is the number of symbols. This storage scheme supports real-time encoding and decoding. In addition, few simple arithmetic operations are performed on the chip for encoding and decoding. Based on our scheme, we show a design for I-bit symbols. The proposed design requires 256*9 and 64*18-bit memory modules to process 8-bit symbols. The chip occupies a silicon area of 3.5*3.5 mm/sup 2/ using 1.2 micron CMOSN standard library cells. Compared with a known parallel implementation which requires up to 65536 PE's, the proposed architecture leads to a single PE design. It requires significantly less area than the known single PE design. Different Huffman codes can be stored by changing the contents of the memory, without changing the design. >