Institution
Samsung
Company•Seoul, South Korea•
About: Samsung is a company organization based out in Seoul, South Korea. It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 134067 authors who have published 163691 publications receiving 2057505 citations. The organization is also known as: Samsung Group & Samsung chaebol.
Papers published on a yearly basis
Papers
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TL;DR: In this paper, a computational framework was employed to evaluate and screen polyanionic materials as cathode coatings, focusing on their phase stability, electrochemical and chemical stability, and ionic conductivity.
233 citations
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TL;DR: By combining all the optimization techniques carefully, the proposed high-performance NAND flash-based storage system has shown 3.6 times higher overall performance compared to the conventional single-channel architecture.
233 citations
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TL;DR: In this paper, an investigation of 3D morphologies for bulk heterojunction (BHJ) films based on regioregular poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) is reported.
Abstract: Here, an investigation of three-dimensional (3D) morphologies for bulk heterojunction (BHJ) films based on regioregular poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) is reported. Based on the results, it is demonstrated that optimized post-treatment, such as solvent annealing, forces the PCBM molecules to migrate or diffuse toward the top surface of the BHJ composite films, which induces a new vertical component distribution favorable for enhancing the internal quantum efficiency (ηIQE) of the devices. To investigate the 3D BHJ morphology, novel time-of-flight secondary-ion mass spectroscopy studies are employed along with conventional methods, such as UV-vis absorption, X-ray diffraction, and high-resolution transmission electron microscopy studies. The ηIQE of the devices are also compared after solvent annealing for different times, which clearly shows the effect of the vertical component distribution on the performance of BHJ polymer solar cells. In addition, the fabrication of high-performance P3HT:PCBM solar cells using the optimized solvent-annealing method is reported, and these cells show a mean power-conversion efficiency of 4.12% under AM 1.5G illumination conditions at an intensity of 100 mW cm−2.
233 citations
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08 Sep 2003TL;DR: In this paper, an n-type GaN layer having a hexagonal pyramid shape is selectively grown on a portion, exposed from an opening of the growth mask, of the underlying N-type GAN layer.
Abstract: A semiconductor light emitting device with improved luminous efficiency is provided. An underlying n-type GaN layer is grown on a sapphire substrate, and a growth mask made from SiO 2 film or the like is formed on the underlying n-type GaN layer. An n-type GaN layer having a hexagonal pyramid shape is selectively grown on a portion, exposed from an opening of the growth mask, of the underlying n-type GaN layer. The growth mask is removed by etching, and then an active layer and a p-type GaN layer are sequentially grown on the entire substrate so as to cover the hexagonal pyramid shaped n-type GaN layer, to form a light emitting device. An n-side electrode and a p-side electrode are then formed.
233 citations
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18 Jul 2002TL;DR: In this paper, a wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chips.
Abstract: A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.
232 citations
Authors
Showing all 134111 results
Name | H-index | Papers | Citations |
---|---|---|---|
Yi Cui | 220 | 1015 | 199725 |
Hyun-Chul Kim | 176 | 4076 | 183227 |
Hannes Jung | 159 | 2069 | 125069 |
Yongsun Kim | 156 | 2588 | 145619 |
Yu Huang | 136 | 1492 | 89209 |
Robert W. Heath | 128 | 1049 | 73171 |
Shuicheng Yan | 123 | 810 | 66192 |
Shi Xue Dou | 122 | 2028 | 74031 |
Young Hee Lee | 122 | 1168 | 61107 |
Alan L. Yuille | 119 | 804 | 78054 |
Yang-Kook Sun | 117 | 781 | 58912 |
Sang Yup Lee | 117 | 1005 | 53257 |
Guoxiu Wang | 117 | 654 | 46145 |
Richard G. Baraniuk | 107 | 770 | 57550 |
Jef D. Boeke | 106 | 456 | 52598 |