Samsung

About: Samsung is a company organization based out in Seoul, South Korea. It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 134067 authors who have published 163691 publications receiving 2057505 citations. The organization is also known as: Samsung Group & Samsung chaebol.

Bottom-Gate Gallium Indium Zinc Oxide Thin-Film Transistor Array for High-Resolution AMOLED Display

Abstract: The fabrication process and the characteristics of bottom-gate Ga2O3-In2O3-ZnO (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 cm2/V ldr s and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.

Wafer level stack structure for system-in-package and method thereof

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

Semiconductor light emitting device, method of manufacturing the same, and semiconductor light emitting device package using the same

Abstract: There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and insulating layer, a first electrode layer, and a conductive substrate sequentially laminated, wherein the second electrode layer has an exposed area at the interface between the second electrode layer and the second conductivity type semiconductor layer, and the first electrode layer comprises at least one contact hole electrically connected to the first conductivity type semiconductor layer, electrically insulated from the second conductivity type semiconductor layer and the active layer, and extending from one surface of the first electrode layer to at least part of the first conductivity type semiconductor layer.

TOPS: new DOA estimator for wideband signals

Abstract: This paper introduces a new direction-of-arrival (DOA) estimation algorithm for wideband sources called test of orthogonality of projected subspaces (TOPS). This new technique estimates DOAs by measuring the orthogonal relation between the signal and the noise subspaces of multiple frequency components of the sources. TOPS can be used with arbitrary shaped one-dimensional (1-D) or two-dimensional (2-D) arrays. Unlike other coherent wideband methods, such as the coherent signal subspace method (CSSM) and WAVES, the new method does not require any preprocessing for initial values. The performance of those wideband techniques and incoherent MUSIC is compared with that of the new method through computer simulations. The simulations show that this new technique performs better than others in mid signal-to-noise ratio (SNR) ranges, while coherent methods work best in low SNR and incoherent methods work best in high SNR. Thus, TOPS fills a gap between coherent and incoherent methods.

Lithium rechargeable battery

Abstract: A lithium rechargeable battery in which an anti-rotation groove is integrally formed with a lower recess of a safety vent at a lower surface of a cap plate, and an insulating plate and a terminal plate rest in the anti-rotation groove so that the terminal plate is prevented from rotating when a cap assembly is assembled is provided In addition, instead of the anti-rotation groove, a resting recess is formed on a lower surface of the cap plate, and the insulating plate and the terminal plate rest in the resting recess, so that the terminal plate is prevented from rotating when the cap assembly is assembled