Samsung

About: Samsung is a company organization based out in Seoul, South Korea. It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 134067 authors who have published 163691 publications receiving 2057505 citations. The organization is also known as: Samsung Group & Samsung chaebol.

Review of non-platinum anode catalysts for DMFC and PEMFC application

Abstract: Articles devoted to non-platinum anode catalysts for DMFC and PEMFC application, operated in acidic media were reviewed. Several classes of possible platinum substitutes based on transition metal carbides, oxides, alloys and new exotic catalysts were described, with focus on synthetic methods, corrosion stability and activity in reactions of methanol/hydrogen oxidation. Directions for future research in field of non-platinum anode materials were discussed.

A General 3-D Non-Stationary 5G Wireless Channel Model

Abstract: A novel unified framework of geometry-based stochastic models for the fifth generation (5G) wireless communication systems is proposed in this paper. The proposed general 5G channel model aims at capturing small-scale fading channel characteristics of key 5G communication scenarios, such as massive multiple-input multiple-output, high-speed train, vehicle-to-vehicle, and millimeter wave communications. It is a 3-D non-stationary channel model based on the WINNER II and Saleh-Valenzuela channel models considering array-time cluster evolution. Moreover, it can easily be reduced to various simplified channel models by properly adjusting model parameters. Statistical properties of the proposed general 5G small-scale fading channel model are investigated to demonstrate its capability of capturing channel characteristics of various scenarios, with excellent fitting to some corresponding channel measurements.

Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature

Abstract: Integrated circuit devices include a first dielectric layer, an electrically insulating layer on the first dielectric layer and an an aluminum oxide buffer layer formed by atomic layer deposition (ALD) and stabilized by heat treatment at a temperature of less than about 600° C., between the first dielectric layer and the electrically insulating layer. The first dielectric layer may comprise a high dielectric material such as a ferroelectric or paraelectric material. The electrically insulating layer may also comprise a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). To provide a preferred integrated circuit capacitor, a substrate may be provided and an interlayer dielectric layer may be provided on the substrate. Here, a metal layer may also be provided between the interlayer dielectric layer and the first dielectric layer. The metal layer may comprise a material selected from the group consisting of Pt, Ru, Ir, and Pd.

Semiconductor devices and methods of manufacturing the same

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Loss Surfaces, Mode Connectivity, and Fast Ensembling of DNNs

Abstract: The loss functions of deep neural networks are complex and their geometric properties are not well understood. We show that the optima of these complex loss functions are in fact connected by simple curves, over which training and test accuracy are nearly constant. We introduce a training procedure to discover these high-accuracy pathways between modes. Inspired by this new geometric insight, we also propose a new ensembling method entitled Fast Geometric Ensembling (FGE). Using FGE we can train high-performing ensembles in the time required to train a single model. We achieve improved performance compared to the recent state-of-the-art Snapshot Ensembles, on CIFAR-10, CIFAR-100, and ImageNet.