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Institution

SDM College of Engineering and Technology

About: SDM College of Engineering and Technology is a based out in . It is known for research contribution in the topics: Diesel fuel & Combustion. The organization has 350 authors who have published 351 publications receiving 2399 citations.


Papers
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Book ChapterDOI
01 Jan 2019
TL;DR: The proposed system deals with addressing the consequences of hybrid system, which employs low rank matrix SVD and a modified variable vector quantization matrix DCT in image compression and proves to be better technique over the SVD-DCT hybrid method.
Abstract: The advent of modern image processing concepts and cutting edge solutions, various architectures of image compression have reached every individual electronic gadgets and embedded systems. Many such designs were suggested and tried, gratifying the present day requirements of electronic industry. On these grounds, the proposed system deals with addressing the consequences of hybrid system, which employs low rank matrix SVD and a modified variable vector quantization matrix DCT in image compression. The efficiency of such proposed system is evaluated with the help of MSE, PSNR, CR, bpp and percentage space saving. DCT alone proves to be better technique over the SVD-DCT hybrid method.

4 citations

Book ChapterDOI
01 Jan 2020
TL;DR: Automatic bottle filling using programmable logic controller (PLC) constitutes a user-specified volume selection, in which the user can input the desired amount of liquid or water to be inserted in the bottles.
Abstract: Automatic bottle filling using programmable logic controller (PLC) constitutes a user-specified volume selection, in which the user can input the desired amount of liquid or water to be inserted in the bottles. It is generally used where many bottles of same volume are to be filled by passing bottles over the conveyor belt. PLC is a main functional block in the automation which tries to minimize the complexity and increases safety and cost reduction. Using of PLC in filling the bottles allows us to select the required amount of liquid by the ladder language. Filling is done by using motor, sensors, conveyor belt, PLC, solenoid valve, and so on. The whole system is more flexible and time saving. The process of filling is carried out for packaging of liquid and beverages. This is an interdisciplinary branch of engineering which includes mechanical, computer, and electronics parts. The process also enhances the knowledge of fabrication, programming, design, planning, and presentation skills. The PLC is gaining popularity because it is easy for troubleshooting which makes programming easier and reduces downtime.

4 citations

Journal ArticleDOI
TL;DR: Improvement with respect to accuracy and computational speed compared to standard NLM is achieved and qualitative and quantitative comparisons show that the proposed method is consistently superior compared to that of NLM and some of its variants.
Abstract: The aim of this paper is to improve both accuracy and computational efficiency of non-local means video (NLMV) denoising algorithm. A technique of principal component analysis (PCA) is used to reduce the heavy dimensionality of patches. A pre-processing step of shot boundary detection is used to split the video sequence into different shots having content-wise similar frames. Further PCA is computed globally for these shots. To speed-up the denoising process, weights are computed in reduced subspace. In the proposed method, we modify the original histogram difference (HD) technique such that content-wise similar frames are separated more systematically and accurately. We have achieved improvement with respect to accuracy and computational speed compared to standard NLM. Moreover, qualitative and quantitative comparisons show that the proposed method is consistently superior compared to that of NLM and some of its variants.

4 citations

Proceedings ArticleDOI
01 Oct 2017
TL;DR: From the detailed simulation results and analysis, one can excavate the routing protocol that performs better depending on the number of nodes, which is based on network throughput, average end to end delay and average jitter.
Abstract: Wireless sensor networks (WSNs) are nowadays implemented in so many fields. In order to guarantee an optimum use of this technology, one need to test different routing protocols performances. This paper evaluates ad hoc on demand distance vector protocol (AODV), dynamic source routing protocol (DSR)'s and Dynamic MANET On Demand (DYMO) performances for IEEE 802.15.4/ZigBee. The evaluation is based on network throughput, average end to end delay and average jitter. Various simulation scenarios are simulated with varying various properties. The network simulator QUALNET (7.4) is used. From the detailed simulation results and analysis, one can excavate the routing protocol that performs better depending on the number of nodes.

4 citations

Journal ArticleDOI
TL;DR: This paper proposes FPGA implementation of optimized Karhunen–Loeve transform for image processing applications and the performance is compared with respect to hardware utilization and accuracy of various existing techniques to prove the efficiency.
Abstract: The various transformation techniques play vital role in the field of Digital Image Processing. In this paper, we propose FPGA implementation of optimized Karhunen–Loeve transform for image processing applications. The Data Format Conversion block is introduced to represent the input data to suitable format and are fed to the Covariance computation block to calculate corresponding covariance values with accuracy. The Optimized Square Root block has been designed in the Eigenvalue computation block to obtain eigenvalues which are in turn fed to the Eigenvector computation block to produce eigenvectors using Modified divider. Further the Karhunen–Loeve Transformed matrix of the input data is obtained by performing multiplication of eigenvectors with covariance values in the matrix multiplication block. The errors are introduced due to fixed point binary calculations and are minimized by novel Error correction block. The proposed architecture is tested on Sparan-6 (XC6SLX45-3CSG324) FPGA board. The performance of the architecture is compared with respect to hardware utilization and accuracy of various existing techniques to prove the efficiency.

4 citations


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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20225
202145
202034
201936
201834
201742