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Institution

Sigrity

About: Sigrity is a based out in . It is known for research contribution in the topics: Decoupling capacitor & Signal. The organization has 44 authors who have published 30 publications receiving 239 citations.

Papers
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Journal ArticleDOI
TL;DR: In this article, the authors proposed a closed-form expression for the parasitics associated with the interconnects of the decoupling capacitors of a dc power distribution network.
Abstract: Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it Full-wave methods are often employed to study the power integrity problem While full-wave methods can be accurate, they are time and memory consuming The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived This allows both frequency and transient responses to be done with SPICE simulation

113 citations

Patent
Jiayuan Fang1
02 Oct 1998
TL;DR: In this paper, a multi-level printed circuit board (PCB) containing at least one power plane for conducting and distributing electrical power and at least ground plane, spaced apart from the power plane, for providing and distributing an electrical ground.
Abstract: The present invention is a multi-level printed circuit board (PCB) containing at least one power plane for conducting and distributing electrical power and at least one ground plane, spaced apart from the power plane, for providing and distributing an electrical ground. At least one integrated circuit chip is mounted on the printed circuit board. At least one signal plane is spaced apart from both the power plane and the ground plane, for conducting and distributing electrical signals from a first point to a second point. The signal plane(s) each have a portion or "patch" that is electrically isolated from signal traces in the remainder of the signal plane. The patches are placed in the area underneath the integrated circuit chip. The patches are connected, respectively, to the power plane or to the ground plane, for reducing effective inductance and input impedance. The multi-level PCB has one or more plated through hole vias for connecting the power or ground plane to a patch. Decoupling capacitors may be provided between the sets of plated through hole vias to further reduce input impedance.

60 citations

Proceedings ArticleDOI
Jin Zhao1, O.P. Mandhana
25 Oct 2004
TL;DR: A fast power delivery system input impedance evaluation methodology for printed circuit board decoupling capacitor placement study is presented in this paper, the methodology is based on electrical network admittance matrix properties, and is rigorously validated by comparing the decoupled capacitor placement evaluation of a real PCB by both impedance matrix and results from commercial electromagnetic field software.
Abstract: A fast power delivery system input impedance evaluation methodology for printed circuit board decoupling capacitor placement study is presented in This work The methodology is based on electrical network admittance matrix properties The admittance matrix methodology described in This work is rigorously validated by comparing the decoupling capacitor placement evaluation of a real printed circuit board by both impedance matrix and results from commercial electromagnetic field software

7 citations

Journal ArticleDOI
TL;DR: A fast and efficient adaptive algorithm for computing the response of microwave circuits over a wide frequency band by using a binary-tree structure and constructs the currents induced on the circuit by using characteristic basis functions, thus obviating the need to repeatedly solve a large method of moments matrix system at each frequency point.
Abstract: A fast and efficient adaptive algorithm for computing the response of microwave circuits over a wide frequency band is introduced in this paper. The algorithm uses a binary-tree structure for sweeping the frequency and constructs the currents induced on the circuit by using characteristic basis functions, thus obviating the need to repeatedly solve a large method of moments matrix system at each frequency point. The implementation of the proposed algorithm is quite simple and can be readily integrated into existing electromagnetic simulation software modules. Numerical results are presented for two test cases demonstrating the accuracy and computational efficiency of the proposed technique.

7 citations

Patent
Jian Liu1, Jiayuan Fang1
28 Jun 2011
TL;DR: In this paper, the authors provide an electromagnetic simulation framework for simulating the electronic packaging structure that includes at least two planes and an interconnect transitional component, which includes solvers for simulation based on parallel-plate, strip line, and microstrip line modes.
Abstract: Methods, systems, and computer-readable media for simulating an electronic packaging structure are disclosed. The methods include providing an electromagnetic simulation framework for simulating the electronic packaging structure that includes at least two planes and an interconnect transitional component. The framework includes solvers for simulation based on parallel-plate, strip line, and microstrip line modes. The method also includes defining ports of the component based on modes, computing a network function characterizing the properties of the component; and associating ports with solvers of the framework.

7 citations


Authors

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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20131
20121
20118
20102
20095
20083