Sony Broadcast & Professional Research Laboratories

About: Sony Broadcast & Professional Research Laboratories is a company organization based out in Taipei, Taiwan. It is known for research contribution in the topics: Signal & Image processing. The organization has 38708 authors who have published 63864 publications receiving 865637 citations.

Plasma system comprising hollow mesh plate electrode

Abstract: A plasma system which eliminates damage derived from charged particles in the plasma and which is able to perform uniform plasma CVD and plasma etching on a large area substrate, wherein a mesh plate having a plurality of holes is placed at the interface of a plasma generation chamber and a substrate treatment chamber which holds a substrate, a high frequency electrical field being applied between an upper electrode in the plasma generation chamber and the mesh plate so as to disassociate the plasma forming gas by electrodischarge so as to cause the generation of plasma. By this, the plasma is isolated from the substrate. On the other hand, source gas supply ports are opened near the holes of the mesh plate, the source gas being introduced from there being brought into contact with the plasma through the holes, whereby the reaction product can be uniformly produced in a broad area. If the reaction product is a deposit-like substance, plasma CVD becomes possible, while if of the etching type, plasma etching becomes possible.

Subtitle encoding/decoding method and apparatus

Abstract: Subtitle searching is achieved by encoding a subtitle to be displayed exclusively during a trick playback mode. Addresses for the subtitle to be played back during the trick playback mode are stored on a record medium reserved for addresses. A computer-readable memory directs a computer to retrieve these addresses and locate subtitles to be displayed during the trick playback mode on the record medium. The subtitles are searched by decoding and displaying the subtitles located at the addresses on the record medium to be displayed during the trick playback mode.

Image processing apparatus, image pickup apparatus, image processing method, and program

Abstract: There is provided an image processing apparatus including an HDR (High Dynamic Range) processing unit inputting images picked up while exposure control that changes an exposure time is being carried out with a predetermined spatial period and a predetermined temporal period on pixels that compose an image sensor, and carrying out image processing. The HDR processing unit generates a first combined image by combining pixel values of a plurality of images with different sensitivities generated by an interpolation process using a plurality of consecutively picked-up images, generates a second combined image by combining pixel values of a plurality of images with different sensitivities generated by an interpolation process that uses a single picked-up image, and generates an HDR image by executing a pixel value blending process on the first combined image and the second combined image in accordance with a blending ratio calculated in accordance with movement detection information.

Semiconductor NAND type flash memory with incremental step pulse programming

Abstract: A semiconductor nonvolatile memory device enabling high speed, high precision data programming and have a large disturb margin, that is, a NAND type flash memory wherein the programming operation is performed by repeating a programming operation a plurality of times through a verify read operation, where the programming word line voltages VPP1 to VPPk and an intermediate prohibit voltage VM1 to Vmk are set to values which are incremented along with an increase of the number k of programming and where the voltage increments of the intermediate prohibit voltage for each increase of the number of programming is set to half of the voltage increments of the programming word line voltage for each increase of the number of programming. Due to this, high speed, high precision data programming becomes possible and further the degradation of the disturb margin can be eliminated.

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

Abstract: In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed a special circuit architecture that we call twisted-binary decision diagram (BDD), where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.