Showing papers by "STMicroelectronics published in 1976"

Symmetrical cell layout for static RAM

Abstract: A symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed. A common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry. Corresponding components of contiguous cells in each row and column are symmetrically disposed with respect to each of the first and second axes of symmetry. In a preferred embodiment, the principal components of each cell include a plurality of insulated gate field-effect transistors each having a source diffusion region and a drain diffusion region formed within the substrate and a plurality of impedance devices electrically connecting the common drain supply node to the drain diffusions of the transistors in each cell. The impedance devices extend radially from the common drain supply node into the interior of each cell, and at least one of the diffused regions of each transistor in each cell is formed in common with a diffused region of a transistor of a contiguous cell.

Dynamic random access memory system

Abstract: An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a variable resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V DD . When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other digit line. As a result, one of the digit lines has a slightly higher voltage than the other. The first set of transistors permit the latching node to be very rapidly brought to ground in order to completely discharge the digit line having the lower voltage, while maintaining substantially the initial high voltage on the other digit line. The common gate nodes of the first transistors are precharged to the drain supply voltage when one of the true or complement digit lines in each column is low and then isolated to provide bootstrapping above V DD when the digit lines are subsequently precharged to the drain supply voltage of the system. The split digit lines are precharged from a common node through a first pair of transistors, with the common node being charged through a third transistor. The third transistor is turned off before the first pair of transistors to prevent noise in the drain supply voltage from resulting in uneven voltage precharges on the split data lines.