Showing papers by "STMicroelectronics published in 1980"

Method for fabricating a semiconductor read only memory

Abstract: A process is disclosed for manufacturing a read only memory in which the specified bit pattern is fabricated into the memory at a late stage in the manufacturing cycle. Before the bit pattern is implanted into a ROM memory cell device (10), the cell is fabricated such that a substrate (12) has source (38) and drain (40) regions therein. A gate oxide (28) is positioned above the channel region of the device (10). A poly gate (30) is positioned immediately above the gate oxide (28) and below an oxide insulating layer (42). A further layer (45) of silicon dioxide is fabricated above the insulating layer (42). Metal contacts (48, 50) are fabricated to be in contact with the source region (38) and drain region (40) of device (10). A masking oxide (56) is deposited over the entire surface of the device (10). To incorporate the desired bit pattern a selected cell is ion-implanted to raise the voltage threshold of the cell. After masking with the customer pattern the insulating layer (45) is completely etched through and the insulating layer (42) is partially etched through above the poly gate (30a). An ion stream (60) is projected into the device (10) with sufficient energy to force the ions through the partially etched layer of silicon dioxide (42) plus the poly gate (30) and gate diode (28) into the channel region of the substrate (12). After the implant step is completed, a layer (64) of top glass is applied to cover the surface of device (10). The glass (64) is then etched to provide openings for bonding pads. The read only memory can be fabricated and parametrically tested before the bit pattern is implanted and only a few manufacturing steps are required to complete the fabrication of the memory after the ion-implantation.

Method of making a plurality of MOSFETs having different threshold voltages

Abstract: An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs. By repeated masking and implanting steps, selected MOSFETs are implanted with differing doses of ions and combinations of doses, thereby forming circuit portions with MOSFETs having threshold voltages tailored to optimize different characteristics associated with different circuit portions.

Dynamic ratioless circuitry for random logic applications

Abstract: A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.

Single electrode sense circuit for charge-coupled transversal filters

Abstract: A charge coupled device transversal filter having split electrodes each having a sense portion and a complementary dummy portion. All electrode sense portions are coupled to a single sense line and all dummy portions are connected to a reference voltage. Tap weights are determined by relative lengths of successive sense portions and weighted samples are taken by shifting charge packets from one sense electrode position to a second while sensing the difference in displacement charge induced in successive sense electrodes. The structure is less sensitive to manufacturing tolerances than earlier structures and provides a sense signal with essentially no common mode component to a sense amplifier.