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Showing papers by "STMicroelectronics published in 1984"


Patent
24 Sep 1984
TL;DR: In this paper, a short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as VT falloff and with a reasonable source-drain operating voltage support.
Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as VT falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

79 citations


Patent
02 Nov 1984
TL;DR: In this article, a phase-locked loop was constructed on a single chip and no external components are necessary, and the closed-loop stability was shown to be maintained without further trimming.
Abstract: An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convertor (14) including two transistor current sources (19,24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as a control voltage to a voltage controlled oscillator (12). The oscillator output is fed by way of a divider to the phase comparator (7) and also provides the high frequency input timing signal for a logic device, such as a microcomputer (2). As the timing apparatus is fabricated using MOS technology, it is not possible to forecast its performance accurately. Surprisingly, it has been found that the timing apparatus of the invention is capable of exhibiting closed loop stability without further trimming. However, to ensure that such closed loop stability can always be obtained, additional components, for varying the parameters of the circuits may be provided, said components being connectible into the circuit by programmable switches, such as laser fuses (as 33, 42).

65 citations


Patent
27 Feb 1984
TL;DR: A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus as mentioned in this paper.
Abstract: A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

26 citations


Patent
Henry H. Eck1
14 Feb 1984
TL;DR: In this article, a technique for redundantly encoding data for synchronous or asynchronous serial transmission or recording and the correlative technique for decoding the serial bit stream are disclosed, which involves making the second data string of a data string pair the complement of the first data string and formatting to the format H 1 Data H 2 Data where H 1 and H 2 are headers wherein at least one bit is the same in corresponding bit positions of the headers.
Abstract: A technique for redundantly encoding data for synchronous or asynchronous serial transmission or recording and the correlative technique for decoding the serial bit stream are disclosed. The encoding technique involves making the second data string of a data string pair the complement of the first data string and formatting to the format H 1 Data H 2 Data where H 1 and H 2 are headers wherein at least one bit is the same in corresponding bit positions of the headers. Decoding involves first detecting the headers and then checking to confirm that the data fields are complements. Also disclosed is a technique for extracting bits from the data stream.

23 citations


Patent
06 Jan 1984
TL;DR: In this article, a redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated.
Abstract: A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.

22 citations


Patent
02 Nov 1984
TL;DR: In this paper, a microcomputer comprising memory 60 and a process is arranged to execute a plurality of concurrent processes and share its time between them, and each process has an allocated priority and a separate linked list is formed for each priority.
Abstract: A microcomputer comprising memory 60 and a process is arranged to execute a plurality of concurrent processes and share its time between them. The microcomputer includes as register (51) for indicating a current process as well as a collection of processes awaiting execution. Each process has a memory location 66 to provide an indication of a next process in a linked list of processes. Each process has an allocated priority and a separate linked list is formed for each priority. A register (53) indicates the front of one list and a further register (52) indicates the end of that list.

20 citations


Patent
11 Apr 1984
TL;DR: In this article, the authors describe concurrent processes with synchronized communication between pairs of processes, where each communicating process has program instructions including one communication instruction to output or input data, and the processes executed by a processor are scheduled by identifying a collection awaiting execution and descheduled by interrupting execution of instructions by the process.
Abstract: A microcomputer system with a processor and memory operates concurrent processes with synchronized communication between pairs of processes. Each communicating process has program instructions including one communication instruction to output or input data. The processes executed by a processor are scheduled by identifying a collection awaiting execution and descheduled by interrupting execution of instructions by the process. A communication channel is used to hold a value indicating whether or not either of a pair of communicating processes has yet executed an instruction requiring communication through that channel. Each communicating process tests the channel contents, and if the other communicating process has not yet reached the corresponding communication instruction, the process is descheduled until both processes have reached corresponding program stages.

19 citations


Patent
25 Apr 1984
TL;DR: In this article, the columns of a memory array are accessed by a plurality of column decoders, each decoder selectively accessing one column in a respective group of columns, and the conditon of each pair of first and second transistors is controlled by way of a respective normally closed fuse, and generally each column decoder is connected by its first transistor only to its respective data line.
Abstract: The columns of a memory array are accessed by a plurality of column decoders, each decoder selectively accessing one column in a respective group of columns. Each column decoder can be connected to a respective data line by way of a first transistor, and the data line can also be connected to the decoder of a preceding group of columns by way of a second transistor. The second transistor associated with the first stage can connect the first data line to a spare column decoder accessing a spare group of columns. The conditon of each pair of first and second transistors is controlled by way of a respective normally closed fuse, and generally each column decoder is connected by its first transistor only to its respective data line. However, if defects are found in a group of columns, the associated fuse is blown to isolate that group from its data line. The second transistor is then rendered conductive to connect the data line to the preceding column decoder. Similarly, the data line of each preceding group is connected to the preceding column decoder with the first data line being connected to the spare column decoder.

18 citations


Patent
02 Nov 1984
TL;DR: In this article, the authors describe a method and system for executing a plurality of concurrent processes providing synchronized message transmission so that data is transmitted between a communicating pair of processes when the two processes are at corresponding program stages.
Abstract: A microcomputer method and system for executing a plurality of concurrent processes provides synchronized message transmission so that data is transmitted between a communicating pair of processes when the two processes are at corresponding program stages. The messages may be variable in length and are transmitted by indicating a source address for the data to be transmitted, a destination address for the data, and a count of the number of standard unit lengths of data to be transmitted in the message.

7 citations


Patent
26 Jun 1984
TL;DR: In this article, an integrated read-only memory of the type in which the columns of memory points present a non-negligeable equivalent capacity (Ca), which is used to define a voltage variation on a selected column when a charge current (Iref) is applied to this column, this voltage variation depending on the state of the selected memory point from this columns, and the column being connected to one input of a differential amplifier, the other input of which receives a comparaison voltage, characterized in that the memory is organized in two half-planes, the selection of a
Abstract: 1. An integrated read-only memory of the type in which the columns of memory points present a non-negligeable equivalent capacity (Ca), which is used to define a voltage variation on a selected column when a charge current (Iref) is applied to this column, this voltage variation depending on the state of the selected memory point from this columns, and the column being connected to one input of a differential amplifier, the other input of which receives a comparaison voltage, characterized in that - the memory is organized in two half-planes, the selection of a column of memory points defining in fact as well a column (D1) of memory points in one of the half-planes as a column (D'1) of memory points in the other half-plane, while the selection of a line defines a line either in one or in the other half-plane, but not simultaneously in both planes ; - the defined columns are applied for reading purposes each to one intput of a differential amplifier, the voltage on the defined column of the half-plane in which no line at all is selected constituting the comparaison voltage to which is compared the voltage in the defined column of the half-plane in which a line selected, a charge current being applied to this latter column.

4 citations


Patent
Joseph Borel1
13 Jun 1984
TL;DR: In this article, a method for isolated semiconductor components on a semiconductor wafer of the type used in bipolar technology is described, where polycrystalline silicon (7) is deposited in a recess (10) of a silicon substrate whose walls are insulated by a layer of silicon nitride (6) with the exception of an opening formed in this nitride layer at the bottom of the recess.
Abstract: @ La presente invention concerne un procede de fabrication de composants semiconducteurs isoles sur une plaquette semiconductrice du type utilise en technologie bipolaire. @ The present invention relates to a method for producing isolated semiconductor components on a semiconductor wafer of the type used in bipolar technology. Selon ce procede, du silicium polycristallin (7) est depose dans un evidement (10) d'un substrat de silicium dont les parois sont isolees par une couche de nitrure de silicium (6) a l'exception d'une ouverture (20) formee dans cette couche de nitrure au fond de l'evidement. According to this method, polycrystalline silicon (7) is deposited in a recess (10) of a silicon substrate whose walls are insulated by a layer of silicon nitride (6) with the exception of an opening (20) formed in this nitride layer at the bottom of the recess. Ensuite, le silicium polycristallin est reepitaxie pour devenir du silicium monocristallin par echauffement thermique a partir du "germe" constitue par le silicium sous-jacent dans l'ouverture (20). Then, the polycrystalline silicon is reepitaxie to become monocrystalline silicon by thermal heating from the "seed" formed by the underlying silicon in the opening (20). Application a la fabrication de transistors PNP lateraux. Application to the fabrication of lateral PNP transistors.

Patent
16 Nov 1984
TL;DR: In this paper, a circuitintegre dondes monocrystalline silicon regions (source 14, drain 16, or polycrystalline (grid 18) are covered with tantalum silicide TaSi 2 (zones 28, 30, 32), while the rest of the wafer is covered with a continuous layer of tantalum oxide Ta 2 O 5, particularly on the sidewalls of polycrystaline silicum gates (areas 36 ') and on the field oxide (zone 34').
Abstract: L'invention concerne un circuitintegre dontdes regions de silicium monocristallin (source 14, drain 16), ou polycristallin (grille 18), sont recouvertes de siliciure de tantale TaSi 2 (zones 28, 30, 32) tandis que le reste de la tranche est recouvert d'une couche ininterrompue d'oxyde de tantale Ta 2 O 5 , notamment sur les flancs des grilles de silicum polycristallin (zones 36') et sur l'oxyde epais (zone 34'). A circuitintegre dontdes monocrystalline silicon regions (source 14, drain 16), or polycrystalline (grid 18) are covered with tantalum silicide TaSi 2 (zones 28, 30, 32) while the rest of the wafer is covered with a continuous layer of tantalum oxide Ta 2 O 5, particularly on the sidewalls of polycrystalline silicum gates (areas 36 ') and on the field oxide (zone 34'). Une couche d'alliage d'aluminium (40) vient en contact ponctuellement avec le siliciure de tantale. A layer of aluminum alloy (40) contacts occasionally with tantalum silicide.

Patent
22 Nov 1984
TL;DR: In this paper, the current transducer is coupled to a user's telephone line and supplies a current (IT) proportional to the current of the line (I L ) for current values included between two predetermined threshold values, opposite in sign and equal in absolute value.
Abstract: A telephone circuit for the ring trip detection, including a current transducer circuit (TR) that is coupled to a user's telephone line and supplies a current (IT) proportional to the current of the line (I L ) for current values included between two predetermined threshold values, opposite in sign and equal in absolute value. When these threshold values are reached the current (IT) supplied by the transducers (TR) is maintained constant when the line current (I L ) varies. An integrator (INT) included in the circuit integrates the current supplied by the transducer on one or more full periods of the line voltage. When the result of such an integration is different from zero, the detection circuit can inform the telephone exchange control equipment that the off-hook has taken place.

Patent
09 Mar 1984
TL;DR: In this article, an electrically reprogrammable non-volatile memory, formed in lines and columns of memory points each comprising a floating gate transistor (T1) and two selection transistors (T2 and T3) receiving a common selection signal on their connected gates (GSi), is presented.
Abstract: 1. An electrically reprogrammable non-volatile memory, formed in lines and columns of memory points each comprising a floating gate transistor (T1) and two selection transistors (T2 and T3) receiving a common selection signal on their connected gates (GSi), on of them (T2) being connected between a first column conductor (Dj) and the drain of the floating gate transistor, and the other (T3) being connected between a second column conductor (GCj) and the floating gate transistor, the sources of the floating gate transistors of the same column being connected together by means of third column conductors (Sj), the memory further comprising a line decoder adapted to apply a selection voltage to a given line conductor (GSi) connecting the gates of all the selection transistors of that line, this memory being of the sort in which, during a writing phase, a zero voltage is established on the first column conductors (Dj) of the columns corresponding to the memory points are not selected, the second column conductors (GCj) corresponding to these same columns being left a high impedance or brought to zero voltage, characterized in that it comprises a column decoder connected independently and directly to each of the column conductors and adapted to establish simultaneously, during a single writing phase, a writing potential difference (VH) between the first and the second column conductor, for all the columns corresponding to memory points selected, this potential difference being of a first sign for writing a mch>Omch 1mch< in another given memory point.

Patent
27 Feb 1984
TL;DR: In this article, a system of microcomputers has the capability of converting a computer from a single-chip configuration in which the only ROM is on the single chip, to a multichannel configuration, where the computer includes one or more additional memory chips, which conversion may be done in the course of a program.
Abstract: © 7 A system of microcomputers has the capability of converting a computer from a single-chip configuration in which the only ROM is on the single-chip, to a multi-chip configuration, in which the computer includes one or more additional memory chips, which conversion may be done in the course of a program.

Patent
Powell Jon1
24 Dec 1984
TL;DR: In this paper, a logic circuit with a constant address number signal source and an OR-gate has been proposed to determine whether the A input will go to the low output and the B input to the high output or vice versa.
Abstract: A circuit element incorporating a logic circuit and a constant address number signal source which serves distinguish one circuit element from others that are otherwise similar, has two inputs (A) and (B), a low output (L) and a high output (H). This element utilizes the address portions of respective digital signal bytes provided respectively to its two outputs, to determine whether the A input will go to the low output and the B input to the high output or vice versa. The element includes, in addition to the address source, a detector for null address portions at each output and a switch responsive to the null detector for substituting the internally stored address number for the input address when a null address portion is detected. The logic circuit also includes an equality detector, for comparing the outputs of the respective switches, which cooperates with the null detector for the A input and an AND-gate to produce a control signal when the switch outputs are equal and the null detector for the A input detects a null address portion. Another comparator produces a control signal when the output of the switch controlled by the A input is greater than the output of the other switch. An OR-gate permit a control signal from either of the sources just described to be operative for connecting the A input to the high input and the B input to the low output.