Showing papers by "STMicroelectronics published in 1987"

Electrical transport properties of transition‐metal disilicide films

Abstract: Electrical resistivity in the temperature range of 2–1100 K and Hall‐effect measurements from 10 to 300 K of CoSi2, MoSi2, TaSi2, TiSi2, and WSi2 polycrystalline thin films were studied. Structure, composition, and impurities in these films were investigated by a combination of techniques of Rutherford backscattering spectroscopy, x‐ray diffraction, transmission electron microscopy, and Auger electron spectroscopy. These silicides are metallic, yet there is a remarkable difference in their residual resistivity values and in their temperature dependence of the intrinsic resistivities. For CoSi2, MoSi2, and TiSi2, the phonon contribution to the resistivity was found to be linear in temperature above 300 K. At high temperatures, while a negative deviation from the linearity followed by a quasisaturation was observed for TaSi2, the resistivity data of WSi2 showed a positive deviation from linearity. It is unique that the residual resistivity, ρ(2 K), of the WSi2 films is quite high, yet the temperature depend...

Method for the encapsulation of integrated circuits

Abstract: To encapsulate integrated circuits mounted on continuous dielectrical strips (surface-mounted circuits) it is proposed to transfer mold a thermosetting resin around circuits carried by the strip, the resin being injected outside the parting plane of the mold, contrary to the usual practice in this field. The protection of the circuits is improved while, at the same time, the ability to test the strip is preserved.

Nonvolatile, semiconductor memory device

Abstract: A non volatile EPROM type memory cell is formed, using a p-channel MOS structure with two levels of polycrystalline silicon (1, 2) and a select transistor (20) in series. A fabrication process for such a device is also disclosed.

Process for making structures including e2prom nonvolatile memory cells with self-aligned layers of silicon and associated transistors

Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows in the intermediate oxide layer between the two silicon layers and, before final etching of the two silicon layers and the intermediate oxide, application of a mask formed in such a manner as to superimpose on the second silicon layer in the transistor areas coverings wider than the corresponding windows of the intermediate oxide layer.

Process for manufacturing LDD CMOS devices

Abstract: A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.

Colour graphics control system

Abstract: A color graphics control system for generating red, blue and green analog signals to a raster scan display at a pixel frequency comprises a RAM storing a pluraltiy of digital color values, digital to analog converters for converting the digital color values into analog signals, an interface to permit an external controller to write digital color values into the RAM locations, a timer including a pixel clock and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

Integrated device for shielding charge injection into the substrate, in particular in driving circuits for inductive and capacitive loads

Abstract: This integrated device for shielding injected charges in driving circuits for inductive and/or capacitive loads comprises four integrated structures including a first barrier region with high resistivity which surrounds the buried layer of the epitaxial flyback pocket which may be set at a potential lower than ground on the side of the buried layer which faces the driving circuit pocket; a first charge collecting region provided in the epitaxial flyback pocket; a third low-loss diode structure, formed in an epitaxial pocket which is isolated from the flyback pocket and is arranged between the latter and the driving circuit, and connected so as to clamp the voltage between the epitaxial flyback pocket and the substrate to the diode direct conduction voltage; and, finally, a last barrier structure formed by a charge collecting region connected to the supply voltage.

Fabrication process for eprom cells with oxide-nitride-oxide dielectric

Abstract: The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.

Electrically alterable, nonvolatile, floating gate memory device

Abstract: Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer (9ʹ) in the "injection" area between the silicon (17) (drain region of the device) and the floating gate (19), has an increased thickness in respect of the thickness of the same gate oxide layer (14) over the channel region (15) of the device in order to decrease the parasitic capacitance of the injection area, thus improving the programming threshold voltage characteristics. A method for fabricating the improved memory device is also disclosed.

Current limiter for constant current for switching driving devices

Abstract: The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage (10) receiving at the input a timing clock signal (MCl) at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element (11) connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load (14) fed by the power element, and a current sensor (16,17) generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element (21) connected to the current sensor (16,17) and disabling the drive stage (10) in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.

EEPROM memory cell with a single polysilicon level and a tunnel oxide zone

Abstract: The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.

EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit

Abstract: The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n+ diffusion which is closed and isolated from those of the other cells of the same memory.

A circuit for the linear measurement of a current flowing through a load

Abstract: A circuit (1) for the linear measurement of a current (IL) flowing through a load (RL) comprises a current sensor consisting of a resistor (RN), and a first driver transistor (M1) connected to the load and a second transistor connected to the resistor (RN), either transistors (M1,M2) being field effect transistors interconnected into a current mirror configuration. This circuit (1), whereto the second transistor (M2) is integrated with an area which is n times smaller than that of the first transistor (M1), further comprises an operational amplifier (A1) having its inputs respectively connected to the drain electrodes (D1,D2) of the first and second transistors (M1,M2) to regulate the drain-source voltage (VDS) of the transistors (M1,M2) and enable linear measurement of the load current (IL) irrespective of the operating temperature.

Defective element disabling circuit having a laser-blown fuse

Abstract: A decoder circuit for disabling a defective element in a circuit having redundant replacement elements employs a fuse on a signal path through the decoder circuit from a selection device to a low-impedance output device and a weak default circuit, such as a pull-up transistor, for forcing the state of the output circuit to a low-impedance default state when the fuse is blown.

Process for the formation of a monolithic high voltage semiconductor device

Abstract: The invention concerns a process for formation of a high voltage monolithic semiconductor device that contains at least one power transistor and an integrated control circuit integrated in a single chip. The device is formed by means of a triple epitaxy which utilizes the same doping agent and by growth of the third epitaxial layer with a concentration of impurities greater than the previous ones. By spreading the buried layers till they penetrate inside the third epitaxial layer, collector regions of transistors in the integrated control circuit are obtained free of unwanted intermediate layers or phantom layers caused by the outdiffusion of doping substance present in the heavily doped isolation region with conductivity of the opposite type. Finally PN junctions are formed for the collector region of a power transistor and for the isolation zone of the integrated control circuit, capable of withstanding high voltages.

Multilingual code receivers

Abstract: A telemetry receiver which is capable of automatically recognizing certain incompatible code formats and correctly decoding received data from a remotely located telemetry transmitter is disclosed The specific embodiment is an end of train receiver mounted in the cab of a locomotive which receives encoded transmissions, including encoded brake pipe pressure data, a transmitter mounted on the last car of a train The receiver permits telemetry equipment to be "mixed-and-matched"; that is, the receiver in the locomotive will respond to the transmissions of a telemetry transmitter attached to the last car of the train no matter what the vendor source The telemetry receiver is provided with a microprocessor which analyzes the received transmission The microprocessor is programmed to recognize certain known transmission protocols and formats and then invoke the correct routine for decoding the received data

Linear load current measurement circuit

Abstract: A circuit for the linear measurement of a current flowing through a load which comprises a current sensor consisting of a resistor, and a first driver transistor connected to the load and a second transistor connected to the resistor, both transistors being field effect transistors interconnected into a current mirror configuration, which includes an operational amplifier having its inputs respectively connected to the drain electrodes of the first and second transistors to regulate the drain-source voltage of the transistors and enable linear measurement of the load current irrespective of the operating temperature.

Direct voltage multiplier capable of being integrated into a semiconducting structure

Abstract: A direct voltage multiplier which can be integrated into a semiconducting structure. The multiplier comprises a capacitor which is charged and discharged at the pace of a clock signal, with a depletion-mode MOS transistor mounted as a resistor and enabling the capacitor to be discharged. The invention makes it possible to integrate the multiplier into a semiconducting substrate and can be used, in particular, to control a VD MOS.

Voltage regulator control circuit for a subscriber line interface circuit

Abstract: A Subscriber Line Interface Circuit (SLIC) having a voltage regulator for application thereto of a DC supply voltage V B and connected at the output terminals to an audio transmission line to provide a line current I L and voltage V L for a given resistance load R L on the line, is provided with a control circuit which, by picking up appropriate current and voltage values from the interface circuit, outputs a voltage value which is the equal of the difference between an optimum supply voltage V BF and the supply voltage V B . The control circuit output is connected to the voltage regulator to minimize the voltage V BFK applied to the interface circuit as the transmission line resistance load R L varies, thus minimizing the power dissipated through the interface circuit.

Method for programming data into an electrically programmable read-only-memory

Abstract: L'invention concerne la programmation des memoires mortes electriquement programmables (EPROM, EEPROM) realisees en circuit integre. The invention relates to the programming of electrically programmable read only memories (EPROM, EEPROM) realized in integrated circuit form. Pour optimiser le processus de programmation des informations on prevoit deux etapes, la premiere etape est une etape de programmation classique mais courte, destinee a memoriser les informations pendant une duree relativement courte ; To optimize the information programming process two steps are provided, the first step is a step of vector but short programming for storing information for a relatively short duration; la deuxieme etape est une surprogrammation plus longue mais effectuee de maniere interne au circuit integre, c'est-a-dire que les informations sont lues en memoire et reinscrites aux memes endroits sans qu'il y ait besoin d'appliquer a nouveau ces informations aux entrees du circuit integre. the second step is a longer but over-programming done internally to the integrated circuit, that is to say, the information is read into memory and reinstated the same locations without need to apply this information again the inputs of the integrated circuit.

Fuel measuring system

Abstract: A fuel measuring system of the bubble type is adaptable for use with a plurality of tanks of predetermined differing geometries. The system employs at least two bubbling tubes located at predetermined locations in a tank. A predetermined volume flow of air is made to pass through each tube. Pressure transducers are used to periodically measure the air pressures supplied to the bubbling tubes. Temperature is also periodically sampled, and the pressure and temperature data is used by a microprocessor to make the necessary computations to first determine the averaged normalized air pressure and then the height of the fuel in the tank. In order to correlate the computed value of fuel height with the actual quantity of fuel in the tank, the microprocessor accesses data in a table lookup memory for the particular tank and performs calculations in order to derive the instantaneous volume of fuel in the tank. The instantaneous volume of fuel is then digitally filtered with two time constants, and the results of the digital filtering is used to determine whether fuel is being added to the tank at a rapid rate as in refueling or fuel is being drawn off the tank at a relatively slow rate as when fuel is being supplied to an engine. Depending on the results of the test, an approximate, but stable, value of fuel volume is generated for display.

Integrated digital signal processing circuit for performing cosine transformation

Abstract: Integrated circuits capable of carrying out transformations of the "cosine transformation" type, used more particularly for the digital processing of images with a view to information compression. The versatile and compact circuit architecture involves dividing a bus into sections separated by switches actuated in phase opposition; certain sections are coupled to computing operators, whereas others are coupled to memories serving for reorganizing the order in which the data is presented to the following operators.

Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices

Abstract: This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

Redundancy scheme for multi-stage apparatus

Abstract: A multi-stage apparatus has an input which is coupled to an output by way of a plurality of first stages. The stages are sequentially coupled together to form a chain. A spare stage, which is substantially identical to at least a selected one of said first stages is also provided. The apparatus also includes programmable logic means arranged to uncouple said selected first stage from said chain and to couple said spare stage into said chain such that the input remains coupled to the output by the same number of stages. In this way a redundancy scheme for the multi-stage apparatus is implemented.

Integrated circuit provided with switching elements for changeover to redundancy elements in a memory

Abstract: In an integrated circuit provided with a memory including redundancy elements and fuses for switching-over to the redundancy elements, a supplementary terminal for receiving a high voltage is connected to all the fuses and to a circuit which generates low voltage at the time of programming of the memory and which is capable of presenting high impedance when the high voltage is applied, with the result that the entire current flows through the fuses selected for blowout.

Method of making Bicmos devices

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant). One masking step defines the area for the base implant (18) and the other masking step defines an area of the oxide (30) over the base implant which must be removed to allow contact between the polycrystalline silicon (29), which is suitably doped to provide the emitter, and the base ( 27,27a,28). The base contacts are produced in a semi-self-aligned manner.

Method for decontamination of a chamber used in vacuum processes for deposition, etching and/or growth of high purity films, particularly applicable to semiconductor technology

Abstract: After introducing the products concerned with the process into the chamber and after creating a vacuum in said chamber, said chamber is decontaminated by a series of inflows of non-contaminating gas and subsequent emptying operations.

Encapsulation method for integrated circuits

Abstract: Pour l'encapsulation des circuits integres montes sur bande continue dielectrique (10) (circuits montables en surface), on propose de mouler par transfert une resine thermodurcissable autour des circuits portes par la bande, l'injection de resine se faisant en dehors du plan de joint du moule contraitement a ce qui est habituel dans ce domaine. For the encapsulation of integrated circuits mounted on continuous dielectric strip (10) (surface mountable circuit), a thermosetting resin is proposed to transfer molding around the circuits carried by the tape, the resin injection taking place out of the plane seal the mold contraitement to what is usual in this field. On ameliore la protection des circuits en conservant la testabilite sur bande. circuit protection is improved maintaining testability tape.

Electrically alterable, nonvolatile, floating gate type memory device with reduced tunnelling area and fabrication thereof

Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect of the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to and from the floating gate through an original self-aligned process, which allows to limit the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.

Non-volatile memory with floating grid and without thick oxide

Abstract: Electrically programmable non-volatile memories, more currently known as EPROM memories. The memory according to the invention, using floating grid transistors with injection by hot carriers has an architecture which is different from that of conventional memories. Instead of having each transistor connected between a bit line and a mass line to Vss, here each transistor is connected between two adjacent bit lines; for example, in the drawing annexed, the transistor T12 of which the grid is controlled by the word line LM1, has its source connected to the bit line LB1 and its drain connected to the bit line LB2 immediately adjacent to LB1. Advantages result from such an arrangement from the point of view of size, since isolating the drains of the two adjacent transistors by means of a thick oxide is no longer necessary.