Showing papers by "STMicroelectronics published in 1991"

Solid state event recorder

Abstract: A solid state event recorder having particular application to railroad locomotives has a plurality of interface modules to allow the collection of desired data over a period of time. Radio downloading of the data provided by a telemetry transmitter to wayside receivers is the primary way of downloading data. Alternative data downloading are provided by a removable memory module, a portable wireless data extractor and a laptop computer. The removable memory module is provided with its own backup battery power supply but normally derives its power from an inductive coupling to the solid state recorder. Data is read into the removable memory module from the solid state recorder via an inductive coupling, and data is read out of the removable memory module to the telemetry transmitter via another inductive coupling. Both the portable wireless data extractor and the laptop computer are used for maintenance purposes. The solid state recorder can be configured in a variety of ways and connected together as master and slave. For example, one recorder, acting as a master and functioning as the primary of operational recorder, can be connected to a second recorder, acting as a slave time synchronized with the first recorder. This second recorder can serve as a maintenance recorder for collecting long term data and trouble shooting a particular locomotive.

Method of forming isolated regions of oxide

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Method and apparatus for operating polyphase DC motors

Abstract: A circuit for operating a polyphase dc motor, for example of the type having a plurality of "Y" connected stator coils, has circuitry for unambiguously determining the actual instantaneous position of the rotor of the motor, circuitry for determining a desired rotor position precedent to executing a desired commutation sequence, and circuitry for executing the desired commutation sequence when the circuit for determining the actual instantaneous position of the rotor detects that the rotor is actually in the desired rotor position. The circuitry for unambiguously determining the actual instantaneous position of the rotor includes a back emf amplifier switchably connected to at least one floating coil in accordance with sequence signals received directly from a sequence generator, and circuitry for determining when the voltage received by the back emf amplifier crosses zero from a predetermined direction. In one embodiment, the circuit includes mask circuitry for inhibiting the zero crossing detection circuitry for a predetermined time after a change in the commutation sequence. The mask circuitry includes clocked up and first and second down counters, the second down counter being inhibited to be clocked until the first down counter has reached a predetermined count, and the zero crossing circuitry being inhibited until at least the second down counter has completed its count. When a zero crossing is detected, the count of the up counter is loaded into both the first and second down counter, then the up counter is reset to begin a new commutation period count.

Simple and efficient modeling of EPROM writing

Abstract: A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 mu m. >

Method for forming a metal contact

Abstract: A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

Stimulated emission in Er:Ti:LiNbO/sub 3/ channel waveguides close to 1.53 mu m transition

Abstract: Fabrication and characterisation of Er:Ti:LiNbO/sub 3/ channel waveguides is reported. A lifetime of 2.4+or-0.2 ms has been measured for the /sup 4/I/sub 13/2/ level. In a pump and probe experiment using a high power InGaAsP laser and a tunable DBR laser, a signal increase of 0.75 dB for a transmitted pump power of 4.8 mW was demonstrated.

Brushless direct current motor with minimized current ripple and method

Abstract: A brushless direct current motor with minimized current ripple and a method is disclosed. The motor system includes commutation current control for controlling the rate of turn-off of the current flowing in the phase being turned-off while simultaneously controlling the rate of turn-on of the current flowing in the phases being excited. This minimizes torque ripple in the motor.

Integrated circuit package with laminated backup cell

Abstract: An integrated circuit package encapsulates a memory chip and a laminated backup battery for preserving data in the event of loss of main power supply. The package includes a lead frame assembly encapsulated within a body of non-conductive material, with the memory chip being mounted onto a device support plate on one side of the lead frame. The laminated battery is supported beneath the device support plate on the opposite side of the lead frame. A flat geometry interconnect media connects the electrodes of the laminated backup battery for wire bond interconnection with the positive and negative power input nodes of the memory chip. The interconnect media is in the form of a flexible, laminated strip having a central conductive laminate sandwiched between a pair of insulation laminates. The integrated circuit chip, the laminated battery, the interconnected media, the lead frame assembly and the gold interconnect wires are completely encapsulated within the molded package body.

Security locks for integrated circuit

Abstract: The disclosure relates to integrated circuits and, more particularly, to circuits that use electronic locks to modify the configuration of the circuit, for example to restrict access by the user to certain functions or certain pieces of data of the circuit. There is provision for a first electronic lock capable of being locked or unlocked during a stage for the testing of the integrated circuit and capable of being irreversibly locked after the end of the testing stage, and for a second electronic lock capable of being unlocked only so long as the first lock is unlocked. In this way, the entire circuit can be tested in the form in which it is presented to the user, the locking of the locks being, so to speak, simulated during the test.

A semiconductor memory with multiple clocking for test mode entry

Abstract: of EP0471541An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Method and apparatus for operating polyphase dc motors

Abstract: A circuit for operating a polyphase dc motor, for example of the type having a plurality of "Y" connected stator coils, has circuitry for unambiguously determining the actual instantaneous position of the rotor of the motor, circuitry for determining a desired rotor position precedent to executing a desired commutation sequence, and circuitry for executing the desired commutation sequence when the circuit for determining the actual instantaneous position of the rotor detects that the rotor is actually in the desired rotor position. The circuitry for unambiguously determining the actual instantaneous position of the rotor includes a back emf amplifier switchably connected to at least one floating coil, and circuitry for determining when the voltage received by the back emf amplifier crosses a reference voltage from a predetermined direction. In one embodiment, the circuit, includes mask circuitry for inhibiting the reference voltage crossing detection circuitry for a predetermined time after a change in the commutation sequence. The mask circuitry includes clocked up and first and second down counters, the second down counter being inhibited to be clocked until the first down counter has reached a predetermined count, and the reference voltage crossing circuitry being inhibited until at least the second down counter has completed its count. When a reference voltage crossing is detected, the count of the up counter is loaded into both the first and second down counters, then the up counter is reset to begin a new commutation period count.

Method for starting a motor

Abstract: A method for starting a polyphase motor of the type having a plurality of stator coils and a rotor includes the steps of measuring the rise time of current on each of the stator coils, determining from the rise time measurement the position of the rotor, and determining a coil to apply a voltage to produce maximum startup torque of the motor. Any position ambiguities are resolved by determining the direction of rotation of the motor by applying a voltage to the determined coil sufficient to produce at least a slight rotation of the rotor, remeasuring of the rise time of current on at least a plurality of the rotor coils, and determining a difference between the rise time measurement and remeasurement. The difference indicates the direction which the rotor was rotated.

Integrated circuit package with molded cell

Abstract: An integrated circuit package encapsulates a volatile memory chip and a backup battery for preserving data in the event of loss of main power supply. The package includes a lead frame assembly encapsulated within a body of non-conductive material, with the memory chip being mounted onto a base plate on one side of the lead frame. The battery is supported in offset relation by axial power leads on the opposite side of the lead frame. The integrated circuit chip, the battery, the lead frame assembly and the gold interconnect wires are completely encapsulated within the molded package body.

Programming voltage generator circuit for programmable memory

Abstract: Electrically programmable memories often include an internal circuit for establishing a programming voltage Vpp higher than the supply voltage. This circuit is formed by a charge pump followed by a voltage regulator. Previously, an analog circuit was usually provided behind the regulator to convert the level of voltage Vpp, set up by the charge pump, into a signal with a slow-rising edge (to reduce the constraints on the programmed cells and increase their lifetime). Instead of such analog circuit, the present invention provides a digital control circuit to control the regulator to set up a regulation voltage that rises gradually from a low value up to the desired value Vpp. The digital control circuit comprises counter with k outputs which enables the gradual short-circuiting and unshort-circuiting of the various series-mounted transistors constituting the regulator, thus making the regulation voltage increase slowly.

Semiconductor memory with a sequence of clocked access codes for test mode entry

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Method for testing integrated circuits

Abstract: A substrate is provided as a test fixture for burning-in and testing integrated circuit devices. The substrate contains a plurality of unpackaged integrated circuit dice arranged in a regular matrix of rows and columns. The substrate is partitioned into an array of rectangles which can be easily broken apart. One integrated circuit die is attached in each rectangle. The integrated circuits are bonded to conductive traces in their respective rectangular areas, and the conductive traces are connected to common locations at one side of the substrate. Voltages can be applied to all of the devices simultaneously by contacting the common locations at the edge of the substrate. This allows for burn-in of all integrated circuit devices on the substrate in parallel, after which they can be separated and used individually on printed circuit boards.

Programmable power reduction circuit for programmable logic device

Abstract: According to the present invention, during programming of a programmable logic device, programming in formation corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.

A semiconductor memory with power-on reset controlled latched row line repeaters

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

Method of making SRAM cell and structure with polycrystalline p-channel load devices

Abstract: A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the interconnect layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over a portion of the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.

Field effect transistor structure and method

Abstract: After formation of gate electrodes in a field effect device, first lightly doped drain regions, and opposite contactivity type halo regions, are formed by implant into the substrate. A first thin oxide layer is then formed over the device, followed by an implant of a second lightly doped drain region. The second lightly doped drain region will be spaced further from the channel of the field effect device than the first lightly doped drain region by the thickness of the thin oxide layer. A second oxide layer is then formed over the device, followed by an anisotropic etch back to form sidewall regions alongside the gate electrode of the device. The sidewall regions are used to align the heavy impurity implant for forming source/drain regions.

Zero power ic module

Abstract: An integrated circuit package (10) encapsulates a volatile memory chip (12) and a backup battery (32) for preserving data in the event of loss of main power supply. The package (10) includes a finger lead assembly (20) encapsulated within a body of non-conductive material (30), with a central base support finger lead (28A,28B) being offset within an interconnect region (18). One terminal (32P) of the battery (32) is welded to the offset base finger lead, (28A,28B) and the integrated circuit chip (12) is bonded directly onto the other battery terminal (32N) by a layer of conductive epoxy. The stacked assembly of the integrated circuit chip (12), the battery (32) and the offset base finger lead (28A,28B) is centered longitudinally and vertically within the interconnect region (18) whereby the stacked assembly, including gold interconnect wires (34P), are completely encapsulated within the molded package body (30), without increasing the standoff height of the package.

Sense circuit for reading data stored in nonvolatile memory cells

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC max . The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

1.5-V high-performance SC filters in BiCMOS technology

Abstract: The authors describe two low-voltage switched-capacitor (SC) filters: one can operate from a minimum supply of 1.5 V and the other from a minimum supply of 2 V (for typical parameter values). Both filters use a fully differential architecture and are fabricated in a standard BiCMOS technology. The lowest supply filter, operated from a 2-V supply, has an SNR (signal-to-noise ratio) of 92 dB and a THD (total harmonic distortion) of -70 dB for a 2.4-V/sub pp/ differential signal. Power consumption and area per pole are 60 mu W and 0.18 mm/sup 2/, respectively, with a clock frequency of 447 kHz. The realized filters can be used as building blocks to implement more complex functions, like the active synthesis of a given impedance in line-fed telecom systems. >

Differential output, power, CMOS, operational amplifier

Abstract: A power CMOS operational amplifier with a differential output (Vout-,Vout+), having an intrinsically stable current absorption under rest conditions, comprises two symmetric branches, each comprising a first folded cascode input inverting stage (M1-M10), a level shifting circuit (M11,M12), a second current mirror type noninverting amplifying stage (M13-M18) and a third output inverting stage (M19,M20), constituted by a complementary pair of transistors, connected in a common source configuration between the supply rails and driven by the output (A",B") of the second noninverting stage and by the output (A',B') of the level shifting circuit. Frequency compensation is accomplished by means of two capacitors (Cc1,Cc2) connected between each of the two output terminals (Vout-,Vout+) of the amplifier and the output (A,B) of the first inverting stage (M1-M10) and a node of the output branch of the noninverting current mirror stage (M13-M18). A single common mode feedback network (McM1-McM3) stabilizes both symmetric branches of the amplifier.

Gate overlapping LDD structure

Abstract: A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

Circuit for providing a signal proportional to the average current flowing through coils of a motor operated in both linear and PWM modes

Abstract: A circuit for providing a signal proportional to the average current supplied to the coils of a motor operated in both linear and PWM modes includes a sense resistor across which a voltage representing the current flowing supplied to said coils is developed. The voltage is selectively applied to an output circuit which operates as a low pass filter circuit when drive current is supplied to the coils and as a voltage hold circuit when drive current is not supplied to the coils. The output circuit includes an amplifier connected to receive a voltage produced by the sense resistor when the motor is operated in the linear mode, and a capacitor and a resistor connected in parallel, the capacitor and resistor being connected between an input and an output of the amplifier to operate as a low pass filter circuit. A switch circuit operating in response to PWM signals disconnects the voltage developed across the sense resistor from the amplifier, and disconnects the resistor from the capacitor when drive current is not supplied to the coils to operate as a voltage hold circuit.

Electrostatic discharge protection device for an integrated circuit pad and related integrated structure

Abstract: A circuit for protection from overvoltages of an external electrical connection pad of a circuit integrated in an n type conductivity epitaxial layer formed on a monocrystal semiconductor substrate, comprises a lateral integrated transistor having an emitter connected to said pad, a collector connected to ground and a base connected to said pad across a resistor, and an integrated Zener diode functionally connected between the base and the collector of said transistor.

A semiconductor memory with multiplexed redundancy

Abstract: An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.