Showing papers by "STMicroelectronics published in 1995"

Widely linear estimation with complex data

Abstract: Mean square estimation of complex and normal data is not linear as in the real case but widely linear. The purpose of the paper is to calculate the optimum widely linear mean square estimate and to present its main properties. The advantage with respect to the linear procedure is especially analyzed. >

DSP design tool requirements for embedded systems: a telecommunications industrial perspective

Abstract: This paper describes the trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR)1 and the tools needed to address them. The paper is in three parts: First, we present the results of a three month survey of DSP design practices at BNR. We briefly describe the characteristics of the designs, as well as the DSP design tools used. However, the emphasis is on the main bottlenecks in the design process, and the tools required to address them in the future. Then, we present a proposal for a next generation DSP design environment for telecommunication applications, based on the survey results. Particular emphasis will be given to code generation, system-level simulation, and behavioral synthesis, the three most requested design tools. Finally, we provide a description of FlexWare, an embedded software development system which is being developed internally. This system addresses one important aspect of this next generation environment, namely design tools for application-specific instruction-set processors (ASIP). FlexWare is composed of two main components: CodeSyn, a retargetable microcode synthesis system; and Insulin, a VHDL-based instruction set simulation system.

The importance of molding compound chemical shrinkage in the stress and warpage analysis of PQFPs

Abstract: This paper addresses the use of finite element (FE) techniques to predict residual warpage in plastic quad flat packs (PQFPs) after encapsulation. Experimental measurements of package warpage are used to validate FE models of the packages. Failure to incorporate mold compound chemical shrinkage into the FE analysis leads to erroneous predictions of package warpage. The warpage sensitivity of different packages to changes in downset is presented. The validated FE package models predict stress levels in packages which are 70% greater than those with temperature coefficient of expansion (TCE) shrinkage alone and questions the accuracy of previous simulations which do not include molding compound chemical shrinkage.

Hardware solutions for fuzzy control

Abstract: A large fraction of software designs using microcontrollers is today adopting fuzzy logic algorithms and this fraction is likely to increase in the future. Hardware implementation of fuzzy logic ranges from standard microprocessors to dedicated ASICs and each different approach is targeted to a different application domain or market area. In this paper, we present an overview of the computational complexity of the fuzzy inference process and the various techniques adopted for fuzzy control tasks, highlighting the tradeoffs that can guide a system designer toward correct choices according to application features and cost/performance issues. In addition, we detail three case studies of architectures that address three different market segments in the fuzzy hardware scenario: dedicated fuzzy coprocessors, RISC processors with specialized fuzzy support and application specific fuzzy ASICs. >

Programmable logic device with memory that can store routing data of logic data

Abstract: A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array

Device and a method for storing data and corresponding error-correction information

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Mixed parallel-dichotomic serial sensing method for sensing multiple-levels non-volatile memory cells, and sensing circuit actuating such method

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

Charge pump circuit with feedback control

Abstract: A charge pump circuit with negative current feedback is dislcosed. The charge pump circuit consists of charge pump stages, switch circuits in between the stages, and a feedback loop to control the conductivity of the switch circuit. The conductivity of the switch circuits is controlled by modulating the bias current of the switch circuit which modulates its conductivity. By using the feedback loop to control the conductivity, the output voltage of the charge pump circuit can be regulated.

A new driving circuit for IGBT devices

Abstract: IGBT devices are increasingly used in power electronic equipment due to their high power handling capability. This paper deals with the problems that concern the turn-on, turn-off, and short-circuit of these devices. An optimal new driving circuit is proposed which gives excellent device output performances. Experimental oscillogram traces of transient condition tests are given, which demonstrate the advantages of using the new driving circuit. The suitability of the driving circuit for integration is analyzed. >

Trench MOS-gated device with a minimum number of masks

Abstract: A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Voltage regulator for semiconductor non-volatile electrically programmable memory devices

Abstract: A voltage regulator for electrically programmable non-volatile memory cells includes a gain stage which is supplied a voltage from a voltage booster connected to a supply voltage reference, having an input terminal connected to an output of a voltage divider and an output terminal connected to a pull-up transistor of a pull-up and pull-down differential pair to output the regulated voltage for programming at least one column or bit line of the memory cells. The voltage regulator also includes a second gain stage having an input terminal connected to a second output of the voltage divider. The second stage has an output connected to turn on the pull-down transistor in the complementary pair upon the regulated voltage exceeding a predetermined value.

Nonvolatile memory cell and a method for forming the same

Abstract: A nonvolatile memory having a cell comprising an N+ type source region and drain region embedded in a P- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

A Scalable Single Poly EEPROM Cell for Embedded Memory Applications

Abstract: An increasing number of Integrated Circuits requires the embedding of a limited amount (up to 16-64 kbits) of EEPROM memory For this application, low process complexity, robust structure and good reliability are more important than small cell size In this paper we present the design and characterization of a single poly EEPROM cell, optimized for embedded applications, and characterized by a good shrink potential A cell area of 687?m2 has been obtained in 07?m technology, and electrical characterization has shown the possibility of achieving a programming time of less than 1 ms, while an endurance of more than 10 million cycles has been achieved at 125°C, with a programming time of 2 ms By further shrink of the same basic layout, cell areas of 55?m2 and 44?m2 have been obtained, and the similar programming and endurance performances have been demonstrated

Method and device for uniforming luminosity and reducing phosphor degradation of a field emission flat display

Abstract: Nonuniformities of luminance characteristics in a field emission display (FED) are compensated pixel by pixel by storing a matrix of correction values, determined by testing, and by applying a corrected drive signal through the relative column drive stages. The individual pixel's correction factor that is applied to the corresponding video signal may be stored in digital or analog form in a nonvolatile memory array. Various embodiments are described including the use of a second updatable RAM array wherein pixel's correction factors are calculated and stored at every power-on to provide an opportunity of trimming-up the luminance of the display for compensating long term decline of luminance due to the phosphors ageing process.

Circuit connection in an electrical assembly

Abstract: An electrical assembly comprises an electrical component 11 having an array of contact bumps 18. The component 11 is mounted on a multilayer printed circuit board 12 having a plurality of conducting pins 28 located in holes in the board 12 and having pointed ends 29 projecting above the board and making electrical contact with the bumps 18 on the component 11.

Method for setting the threshold voltage of a reference memory cell

Abstract: A method for setting the threshold voltage of a reference memory cell of a memory device is described, the reference memory cell being used as a reference current generator for generating a reference current which is compared by a sensing circuit of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix of the memory device. The method comprises a first step in which the reference memory cell is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell is verified. The second step provides for performing a sensing of the reference memory cell using a memory cell with known threshold voltage belonging to the memory matrix as a reference current generator for generating a current which is compared by the sensing circuit with the current sunk by the reference memory cell.

A controller for implementing scan testing

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.

MOS technology power device with low output resistance and low capacity and related manufacturing process

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Signal processing circuit to implement a Viterbi algorithm

Abstract: To carry out the processing operations relating to the implementation of a Viterbi algorithm, an integrated circuit comprising a processor and a coprocessor is made. The coprocessor is constructed so as to carry out operations of accumulation, comparison and selection in order to limit or reduce the work of a processor that would have to carry out these operations. By judiciously choosing the structure of the coprocessor, it is possible to make this co-processor sufficiently programmable so that it is suited to various situations of implementation of the Viterbi algorithm.

Modeling of the intrinsic retention characteristics of FLOTOX EEPROM cells under elevated temperature conditions

Abstract: A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells. >

Adaptive optical sensor

Abstract: An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.

Method for forming controlled voids in interlevel dielectric

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.

Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit

Abstract: The disclosure relates to memories in integrated circuit form. A programmable non-volatile memory cell of the bistable type is described. This memory cell can take one stable state or another depending on whether either one of two floating-gate transistors of the cell has been programmed. In the initial state, neither of the two transistors is programmed so that the cell cannot remain in this state and at least one of the transistors has to be programmed. To avoid this, there is provided an additional transistor controlled by the output of the cell to set up imbalance in the cell which can then take a well-determined stable state even if no transistor is programmed, while at the same time ensuring that there is no consumption of current by the cell even in this case. The disclosure can be applied to the redundancy circuits of large-capacity memories to memorize the defective addresses. It makes it possible to avoid having to program the cells when the memory has no defective addresses.

Method for the implementation of modular multiplication according to the Montgomery method

Abstract: A method for the implementation of modular multiplication according to the Montgomery method, wherein a multiplicand A and a multiplier B are encoded respectively on a and b words of k bits, the most significant words of A and B being non-zero, a modulo N is encoded on m words of k bits, the modulo having (m-m') most significant words with k zero bits, with 0

Active hierarchical bitline memory architecture

Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

From total quality management to total quality environmental management

Abstract: Total quality management (TQM) was developed at the same time as the interest in environmental issues began to emerge and, as such, it has built in the same concepts as those regarding issues relevant to the environment. Suggests the acronym in use today, TQEM (total quality environmental management), clearly reflects its genesis and the existing parallelism between quality and environmental problems. In the vision of a TQM‐oriented company in which, by striving for continuous improvement, quality is deployed to everybody, the analogy with the environmental programme is demonstrated by the fact that it is not necessary to convince anyone of the need to operate in a “greener” manner because each person is already convinced of his/her own role in this domain both as an individual and as an employee of the company.

Method and apparatus for starting a sensorless polyphase DC motor in dual-coil mode and switching to single coil mode at speed

Abstract: A method and apparatus for operating a polyphase dc motor selectively in dual-coil or uni-coil commutation modes. The motor has a plurality of "Y" connected driving coils connected together at a center tap. Each driving coil has an input node at an end opposite the center tap, and is driven by a switch pair. Each switch pair is arranged for connection in series across a power supply voltage, and has a node between each switch connected to a respective one of the coil input nodes. An additional pair of switches are provided for connection in series across the power supply with a connection node between each switch connected to the center tap. A circuit is provided to operate the switches to cause a driving current to be passed between sequentially selected pairs of the driving coils for an initial start-up time. Also, a circuit to operate the switches after the initial start-up time is provided to cause a driving current to be passed between sequentially selected only single ones of the driving coils and the center tap current input node. The apparatus also has a circuit for detecting a zero crossing of a bemf signal of a floating one of the driving coils and a delay circuit for establishing a delay between a zero crossing and a commutation of driving signals to the coils. A circuit operates the delay circuit to provide a first predetermined delay in dual-coil mode and a second predetermined delay in uni-coil mode.

Fault detection for entire wafer stress test

Abstract: A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals. During the test the current consumed by each die is monitored and, if a high current is consumed by one die, that die is isolated from the array of dies by controlling the test enable signals present in each row and column of the array. This circuit allows a parallel testing of a plurality of integrated circuits on a single wafer, reduces dramatically test times and avoids consequent burn in of packaged devices.

Testing a non-volatile memory

Abstract: An integrated circuit memory device has: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to the data latches; a set of address latches for holding address bits for addressing the memory array; a test bus; a data bit routing circuit connected to the data latches for selectively routing data bits to either the memory array or the test bus; an address bit routing circuit connected to the address latches for selectively routing address bits to either the array or the test bus; and an output circuit for outputting data bits and address bits on the test bus. In this way, data bits and address bits can be checked for accuracy against the originally supplied data bits and address bits. Thus, a test can be conducted without requiring data actually to be written to memory cells of the memory.

BEMF rectification voltage when power supply energy fails

Abstract: In a disk drive, the read-write heads of the disk drive should be parked during a power failure. The kinetic energy of the spinning rotor is used to move the head away from the disk's surface. A high voltage is produce from the low voltage spindle motor by using a BEMF voltage to step up the voltage in a voltage supply capacitor to a higher voltage by enabling or disabling a switch connected to a comparator. When the switch is turned on, it shorts the rectified voltage in the stator windings to ground in order provide a current path for a current formed in the coils by the BEMF. When the current reaches a predetermined level, the switch is turned off. The current flows through the voltage supply capacitor so that its voltage is "kicked-up" by the inductance of the windings and by the BEMF still present in the stator windings. This increased voltage is used to park the heads and to brake the motion of the spindle. Two control feedback loops are used to more efficiently enable the voltage conversion. A current comparator compares the current in coils to a reference current and turns the switch off when the current is at a predetermined level. A voltage comparator compares the voltage across the load with a reference voltage and turns the switch off when the voltage is above a predetermined value.